Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device

ABSTRACT

Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater ( 102 ), a coating solution containing a thin film component which is supplied from a solution storage section ( 105 ) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section ( 103 ) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.

TECHNICAL FIELD

[0001] The present invention relates to a thin film device including athin film laminate structure such as a thin film transistor (hereinafterreferred to as TFT) and a method for making the same, and in particularrelates to a thin film device capable of low cost production due to adecreased initial investment and a method for making the same. Also, thepresent invention relates to a liquid crystal panel and an electronicdevice using the thin film device.

BACKGROUND ART

[0002] In recent years, liquid crystal display devices using such typesof thin film devices have been used in notebook-type personal computers,car navigation systems, video cameras and various portable informationdevices, and their range of applications and production is drasticallyincreasing. Such phenomena are due to improved performance includingreduced price of the liquid crystal display devices, enlarged screensize, improved image resolution and low electrical power consumption.Further cost reduction is, however, required for further expansion ofthe market and range of applications.

[0003] The mainstream of the liquid crystal devices is active matrixliquid crystal devices using TFTs as switching elements for pixels. Eachliquid crystal device includes TFTs, a TFT substrate on which a matrixof pixel electrodes connected to the TFTs are formed, a countersubstrate provided with a common electrode, and a liquid crystalencapsulated between these two substrates. FIG. 17 shows the mainsection of a TFT substrate 60. In FIG. 17, TFTs 61 are formed at pixelpositions near the intersections of a plurality of source or data signallines S1, S2, . . . Sn arranged in columns with a plurality of gate orscanning signal lines G1, G2, . . . Gm arranged in rows. Sourceelectrodes of the TFTs 61 are connected to their respective sourcelines, and drain electrodes are connected to their respective pixelelectrodes 62. The data signal supplied from a source line is applied toa pixel electrode 62 through its corresponding TFT 61 based on thescanning timing signals supplied through the corresponding gate line.The state of the liquid crystal is changed and driven for displaying byan electric field between the pixel electrode 62 and the commonelectrode, not shown in the drawing.

[0004] The liquid crystal display device is fabricated by panelassembling including encapsulation of the liquid crystal between the TFTsubstrate 60 and the counter electrode, and packaging of drivingcircuits for driving the source lines and the gate lines. The cost ofthe liquid crystal display device greatly depends on the cost of the TFTsubstrate 60. The cost of the TFT substrate 60 depends on themanufacturing method of the TFTs. A part of driving circuits may beformed on the TFT substrate 60 by forming the active elements with theTFTs, and in this case, the cost of the TFT substrate represents a highproportion of the cost of the liquid crystal display device.

[0005] A TFT has a thin film monolithic structure including a pluralityof thin films which include at least a silicon semiconductor layerhaving an insulating layer, a conductive layer, a source, a drain and achannel region. The cost of the TFT greatly depends on the productioncost of the thin film monolithic structure.

[0006] The insulation layer in the thin film monolithic structure isformed by a low pressure chemical vapor deposition (LPCVD) process or aplasma enhanced CVD (PECVD) process, because a normal pressure CVD(NPCVD) process results in low uniformity of the film thickness. Theconductive layer, or typically the metal layer, is formed by asputtering process. The silicon film for forming the siliconsemiconductor layer is also formed by the PECVD or LPCVD process.Further, a method for implanting an impurity into the silicon film by anion implanting process or an ion doping process is used. Alternatively,the high concentration impurity region which functions as a source-drainregion is formed of an impurity-doped silicon film in a CVD system.

[0007] The CVD systems and the sputtering system used in theabove-mentioned film deposition processes belong to vacuum units forprocessing materials under vacuum pressures, and require large vacuumsystems, resulting in an increase in initial investment. In the vacuumsystem, a substrate is transferred to a vacuum evacuation chamber, asubstrate heating chamber, a film deposition chamber and a vent chamber,in that order, to form a film. The substrate atmosphere therefore mustbe changed from open air to vacuum, and this limits the throughput.Because the ion implanter and the ion-doping system are also vacuumsystems, the same problems as above occur. Further, the ion implanterand the ion-doping system require complex mechanisms for generatingplasma, extracting ions, mass-separating the ions (for the ionimplanter), accelerating ions, collimating ions, scanning ions and soon, resulting in a remarkably high initial investment cost.

[0008] As described above, the thin film deposition technology and theprocessing technology for producing a thin film monolithic structure arebasically similar to the manufacturing technology for LSI circuits. Themain means for cost reduction of the TFT substrate include scaling-up ofthe substrate size for forming TFTs, improvement in efficiency of thethin film deposition and its processing step, and improvement in yield.

[0009] Scaling-up of the substrate size for producing large liquidcrystal display devices with reduced costs is an obstacle to high speedtransfer of the substrates in the vacuum system, and causes breakage ofthe substrate due to thermal stress during the deposition steps, henceit is significantly difficult to improve the throughput of the filmdeposition system. Also, the scaling-up of the substrate size inevitablyrequires scaling-up of the film deposition system. An increased costaccompanied by the increased volume in the vacuum system furtherincreases the initial investment, and as a result, it is difficult toachieve drastic cost reduction.

[0010] Although an increased yield is a valuable means for costreduction, a yield near the limit has been achieved, and thus drasticcost reduction is difficult in view of the yield.

[0011] Patterning of each layer is performed by a photolithographicprocess. The photolithographic process essentially includes a coatingstep, an exposure step and a developing step of a resist film. Afterthese steps, an etching step and a resist-removing step are required,hence the steps for patterning is a factor in increasing the number ofsteps for thin film deposition. This is a factor in the increased costof thin film device production.

[0012] Regarding the resist-coating step in the photolithographicprocess, only less than 1% of the resist solution dropped onto thesubstrate remains on the substrate as the resist film after spincoating, reducing the efficiency of the use of the resist solution.

[0013] Although a printing process has been proposed as a low costprocess instead of a large scale exposure system used in the exposurestep, it has not yet reached practical use due to problems such asprocessing accuracy.

[0014] As described above, it is not possible to drastically reduce thecost of the TFT substrate, although the market requires drastic pricereduction of the liquid crystal display devices.

[0015] It is an object of the present invention to provide a thin filmdevice and a method for making the same, in which a part, or all of, thefilms in a thin film monolithic structure used for a liquid crystaldisplay device are deposited without a vacuum system in order todecrease initial investment and operation costs, increase the throughputand significantly decrease the production costs.

[0016] It is another object of the present invention to provide a thinfilm device and a method for making the same, in which a thin filmhaving characteristics similar to those of a CVD or sputtered film isformed of a coating film while achieving cost reduction.

[0017] It is a further object of the present invention to provide a thinfilm device and a method for making the same, in which the consumptionof a coating solution is decreased in the formation of the thin coatingfilm for achieving cost reduction.

[0018] It is still another object of the present invention to provide athin film device and a method for making the same, which is capable ofpatterning the formed film without a photolithographic process and,thus, reducing the cost.

[0019] It is a still further object of the present invention to providea thin film device, a liquid crystal panel and an electronic deviceusing the same, in which a plane in contact with the liquid crystal canbe planarized by forming a pixel electrode with a coating film.

[0020] It is another object of the present invention to provide a thinfilm device, a liquid crystal panel, and an electronic device using thesame, in which a wiring layer can be used as a light-shielding layer fora black matrix and the thin film device has a high aperture ratio.

[0021] It is still another object of the present invention to provide aliquid crystal panel and an electronic device which enable costreduction due to use of an inexpensive thin film device.

DISCLOSURE OF INVENTION

[0022] According to an embodiment of the present invention, a thin filmdevice has a thin film monolithic structure comprising a plurality ofthin films including at least one insulating layer and at least oneconductive layer, wherein

[0023] at least one thin film in the thin film monolithic structure isformed of a coating film (excluding a spin-on-glass film having a basicstructure comprising siloxane bonds), which is obtained by applying asolution containing a constituent of the thin film followed byannealing.

[0024] A method for making the thin film device comprises the followingsteps of:

[0025] applying a coating solution containing a constituent of the thinfilm onto a substrate; and

[0026] forming a coating film (excluding a spin-on-glass film having abasic structure comprising siloxane bonds) by annealing the coatedsurface of the substrate.

[0027] In the present invention, at least one layer in the thin filmmonolithic structure is formed as a coating film without a vacuumsystem. As such a coating film, a spin-on-glass (SOG) film having abasic structure comprising siloxane bonds, which has been used as aplanarization layer, has been known. The organic SOG film is, however,readily etched during an oxygen plasma process, whereas the inorganicSOG film readily cracks even if the film has a thickness of severalthousand angstroms, hence it is rarely used solely as an interlevelinsulating film, and is used as only a planarization layer above a CVDinsulating film.

[0028] In the present invention, an insulating layer and a conductivelayer composing a thin film monolithic structure are formed of a coatingfilm other than the SOG film, and the thin film can be planarized at thesame time. Because the coating film can be formed without a vacuumsystem such as a CVD system or a sputtering system, a mass-productionline can be constructed with a significantly smaller investment comparedto conventional systems, the throughput of the system can be increased,and the cost of the thin film device can be drastically reduced.

[0029] The thin film monolithic structures include various structures,for example, those including semiconductor layers, those including thinfilm transistors, and those including an underlying insulating layer andan upper protective insulating layer.

[0030] In these cases, it is preferable that all of the insulatinglayers contained in the thin film monolithic structure be formed of acoating film. A gate insulating layer requiring a critical film qualityfor ensuring desired thin film transistor characteristics, however, maybe formed by a method other than a coating process.

[0031] It is preferable that at least two thin films in the thin filmmonolithic structure be formed by a coating process in order to reducethe device cost which is a purpose of the present invention.

[0032] The insulating layer can be formed of a SiO₂ coating film, whichis obtained by applying a solution containing a polymer having Si—Nbonds (polysilazane), followed by a first annealing process in an oxygenatmosphere. Because the polysilazane having the above structure exhibitshigh cracking resistance and oxygen plasma resistance, a single layercan be used as an insulating layer having a given thickness.

[0033] It is preferable that the insulating layer be subjected to asecond annealing process at a temperature higher than that in the firstannealing process to further clean its surface. The second annealingprocess may be performed at a high temperature for a short period usinga laser or a lamp.

[0034] The semiconductor layer is formed by implanting an impurity intoa silicon coating film, which is formed by applying a solutioncontaining silicon particles, followed by a first annealing process.

[0035] It is preferable that the semiconductor layer be subjected to asecond annealing process at a temperature higher than that in the firstannealing process to improve the crystallinity in the layer. The secondannealing process may also be performed at a high temperature for ashort period using a laser or a lamp.

[0036] Preferably, a method for diffusing an impurity into the siliconcoating film comprises the following steps of:

[0037] forming by coating an impurity-containing layer onto the siliconcoating film; and

[0038] diffusing the impurity into the silicon coating film by heatingthe impurity-containing layer.

[0039] Conventionally, the high concentration impurity region whichfunctions as a source-drain region has been formed of an impurity-dopedsilicon film by a CVD system, or formed by introduction of an impurityby an ion implanting process or an ion doping process. In the presentinvention, a source-drain region is formed by a step of applying andbaking a solution to form a thin film containing an impurity, and by astep of annealing the thin film at a high temperature for a short periodusing a lamp or a laser to form a high concentration impurity region.The ion implanting system and the ion doping system basically belong tovacuum systems, and require extremely complicated mechanisms forgenerating plasma, extracting ions, mass-separating the ions (for theion implanter), accelerating ions, collimating ions, scanning ions andso on. Hence these two systems have evidential high prices compared tothe system for coating and annealing the thin film containing theimpurity.

[0040] There are two methods for forming the conductive layer. In onemethod a thin metal film is formed and in the other method a thintransparent conductive film is formed.

[0041] The formation of the thin metal film as a conductive layerincludes coating of a solution containing conductive particles and thenevaporating the solvent by a first annealing process. A conductivecoating film can be thereby formed.

[0042] It is preferable that the conductive layer also be subjected to asecond annealing process at a temperature higher than that in the firstannealing process to reduce the resistance of the layer. The secondannealing process may be performed at a high temperature for a shortperiod using a laser or a lamp.

[0043] Preferably, a method for forming a transparent conductive film asa conductive layer comprises:

[0044] a first annealing step annealing the coated surface in an oxygenor nonreductive atmosphere; and

[0045] a second annealing step annealing the coated surface in ahydrogen or reductive atmosphere.

[0046] When forming the transparent electrode as the conductive layer,for example, an organic acid containing indium and tin is used as acoating solution. Preferably in this case, a solvent used for adjustingthe viscosity is evaporated (at, for example, a temperature ofapproximately 100° C.) after coating, and then the above-mentioned firstand second annealing processes are performed. Indium oxide and tin oxideare formed during the first annealing process, and the film is reducedduring the second annealing process in a hydrogen or reductiveatmosphere.

[0047] It is preferable that the temperature in the second annealingprocess be lower than that in the first annealing process.

[0048] The transparent conductive coating film after the first annealingprocess can be prevented from thermal deterioration in the secondannealing process.

[0049] Preferably, the substrate is maintained in the nonoxidizingatmosphere after the second annealing process until the substratetemperature is decreased to 200° C. or less. The reoxidation of thetransparent conductive coating film reduced during the second annealingprocess can be thereby suppressed, and thus the sheet resistance of thetransparent conductive coating film does not increase. It is preferablethat the substrate be introduced into open air at a temperature of 100°C. or less in order to ensure prevention of the reoxidation. Because theresistivity of the coated ITO film decreases in proportion to the oxygendefects in the film, the reoxidation of the transparent conductivecoating film due to oxygen in the open air results in an increase in thespecific resistivity.

[0050] In the formation of the transparent conductive coating film, acoating solution containing indium (In) and tin (Sn) is applied onto thesubstrate. The coating film is oxidized in the first annealing processto form an ITO film. Using the coated ITO film, the conductive layer isalso usable for the transparent electrode.

[0051] When the surface of the ITO film is plated with a metal, the filmcan be used as a conductive layer other than the transparent electrode,and the metal plating can decrease the contact resistance.

[0052] It is preferable that a conductive sputtering film be formed onthe contact face of the coated ITO film by a sputtering process.

[0053] An example of the thin film monolithic structure is an activematrix substrate including pixel switching elements provided on theirrespective pixels, which are formed near intersections of a plurality ofdata lines with a plurality of scanning lines, and pixel electrodesconnected thereto.

[0054] A typical pixel switching element used in the active matrixsubstrate is a thin film transistor. The thin film transistor as thepixel switching element includes a gate electrode electrically connectedto one of the scanning lines and a drain electrode electricallyconnected to one of the pixel electrodes.

[0055] It is preferable that the pixel electrodes be formed of aconductive coating film in such a thin film monolithic structure. Thesurface in which the pixel electrodes are formed generally has steps,while the surface of the conductive coating film is substantiallyplanarized when the pixel electrode is formed of the conductive coatingfilm. As a result, rubbing can be satisfactorily performed andoccurrence of reverse-tilt domains can be prevented.

[0056] It is preferable that the conductive coating film used for thepixel electrodes be a coated ITO film. The coated ITO film functions asa transparent electrode and is suitable for producing an active matrixsubstrate in a transmission liquid crystal display device.

[0057] The thin film transistor as the pixel switching element includesan interlevel insulating film formed on the front surface of the gateelectrode, and the data line and pixel electrode are electricallyconnected to the source region and the drain region, respectively,through contact holes formed in the interlevel insulating film.

[0058] The interlevel insulating film may be composed of a lowerinterlevel insulating film which lies at the lower side, and an upperinterlevel insulating film which is formed on the surface of the lowerinterlevel insulating film. In this case, the data line is electricallyconnected to the source region through a first contact hole formed inthe lower interlevel insulating film. On the other hand, the pixelelectrode is electrically connected to the drain region through a secondcontact hole formed in the lower interlevel insulating film and theupper interlevel insulating film.

[0059] In such a configuration, the data line and the pixel electrodeare formed on different layers from each other, hence these do notshort-circuit each other even if they are formed at a position in whichthey overlap with each other. The periphery of the pixel electrode cantherefore be arranged above the data line and the scanning line.

[0060] As a result, no planar gap is present between the data line orscanning line and the pixel electrode. The data line and the scanningline can therefore function as a black matrix having a light-shieldingfunction. Accordingly, it is not required to form a light shieldinglayer as the black matrix by an additional process.

[0061] Because the range capable of forming the pixel electrode isexpanded, the aperture ratio of the pixel region is increased, resultingin a bright display.

[0062] It is preferable that the pixel electrode formed of a conductivecoating film be electrically connected to the drain electrode through aconductive sputtering film.

[0063] Because the sputtering film has a lower contact resistance thanthat of the conductive coating film, the contact resistance can bereduced by positioning the conductive sputtering film between theconductive coating film and the source region.

[0064] It is preferable the conductive sputtering film be a sputteringITO film so as not to decrease the aperture ratio.

[0065] When the conductive coating film and the conductive sputteringfilm have the same pattern, the accuracy in the patterning of the pixelelectrode can be improved, because a resist film can be formed on onlythe conductive coating film having high adhesiveness to the resist mask,and the conductive coating film and the conductive sputtering film canbe simultaneously patterned. Resist mask formation on the conductivesputtering film having low adhesiveness to the resist mask is notrequired, and a decrease in accuracy in the patterning can be avoided.

[0066] When the conductive coating film and the conductive sputteringfilm do not have the same pattern, it is preferable that the peripheryof the conductive coating film lies outside of the periphery of theconductive sputtering film.

[0067] Resist masks are separately formed on the conductive coating filmand the conductive sputtering film and are separately subjected tosputtering by different steps. The accuracy of the patterning for theperiphery of the pixel electrode depends on the accuracy of thepatterning for the conductive coating film having a larger patterningdimension than that of the conductive sputtering film. The low accuracyof the patterning for the conductive sputtering film having lowadhesiveness to the resist mask does not affect the accuracy of thepatterning for the pixel electrode.

[0068] When the conductive sputtering film and the data line are presentin the same layer, these can be simultaneously formed of the same metalmaterial.

[0069] Alternatively, the conductive sputtering film may lie above thedata line. In this case, as these layers are formed by different steps,these layers may be formed of the same material or different materials.

[0070] The interlevel insulating film may include a lower interlevelinsulating film at the lower side and an upper interlevel insulatingfilm deposited on the surface of the lower interlevel insulating film,and the data line and the conductive sputtering film may be formed onthe surface of the upper interlevel insulating film. The data line iselectrically connected to the source region through a first contact holeformed in the lower interlevel insulating film. On the other hand, theconductive sputtering film is electrically connected to the drain regionthrough a second contact hole formed in the upper interlevel insulatingfilm and the lower interlevel insulating film. The conductive coatingfilm is deposited on the surface of the conductive sputtering film.

[0071] Alternatively, the data line and the conductive sputtering filmmay be formed in the same layer on the surface of the lower interlevelinsulating film. In this case, the data line is electrically connectedto the source region through a first contact hole formed in the lowerinterlevel insulating film. The conductive sputtering film iselectrically connected to the drain region through a second contact holeformed in the lower interlevel insulating film. Further, the conductivecoating film is deposited on the surface of the upper interlevelinsulating film, and electrically connected to the conductive sputteringfilm through a third contact hole formed in the upper interlevelinsulating film.

[0072] In accordance with another embodiment, a liquid crystal panelcomprises:

[0073] an active matrix substrate provided with the abovementioned thinfilm device,

[0074] a counter substrate facing the active matrix substrate, and

[0075] a liquid crystal layer encapsulated between the active matrixsubstrate and the counter substrate.

[0076] In accordance with a further embodiment, an electronic devicecomprises the liquid crystal panel.

[0077] In these cases, the cost reduction in the thin film deviceenables drastic cost reduction of the liquid crystal panel and theelectronic device using the liquid crystal panel.

[0078] In the above-mentioned solution coating step, it is preferablethat the solution be applied to only the coating region on the substrateto form a patterned coating film on the substrate, because aphotolithographic process including many steps is not required.According to this process, consumption of the coating solution decreasesand thus the operation cost can be reduced.

[0079] In accordance with still another embodiment of the presentinvention, a method for making a thin film device is characterized inthat a patterned coating film is formed on the substrate by:

[0080] preparing a coating solution dispenser head provided with aplurality of liquid discharging nozzles, and

[0081] discharging the coating solution onto only the coating region onthe substrate while relatively changing the positions of the substrateand the liquid discharging nozzles.

[0082] This method can be achieved by, for example, an ink jet process.Because the coating solution is not wasted and no photolithographicprocess is required, this method greatly contributes to the investmentcost reduction and improved throughput. For example, in conventionalcoating techniques only approximately 1% of a dropped resist has beenused as a coating film, whereas in the present invention 10% or more ofa dropped resist can be used as a coating film. Of course, such a highcoating efficiency holds for the other coating films in the presentinvention, and thus the reduced use of the coating materials and thereduced time in the coating processes enable the cost reduction ofliquid crystal display devices.

[0083] It is preferable that these nozzles be independently controlledto discharge or not to discharge the coating solution, and positions ofthe substrate and the discharge nozzles be relatively changed whilecontrolling the coating timing on the nozzle. More precise patterncoating can thereby be achieved.

[0084] Such a coating process is applicable to coating of variouscoating solutions for forming coating films by other than coating of theresist for forming a resist pattern. For example, if an insulatingcoating film is pattern-coated, a contact hole can be formedsimultaneously with the coating.

[0085] As described above, in accordance with the present invention, apart or all of the thin films can be formed by applying and annealing asolution, hence a thin film device can be produced with an inexpensiveproduction unit having a high throughput.

BRIEF DESCRIPTION OF DRAWINGS

[0086]FIG. 1 is a block diagram of a coating film deposition unit usedin a first embodiment in accordance with the present invention;

[0087]FIG. 2 is a block diagram of another coating film deposition unitused in a first embodiment in accordance with the present invention;

[0088]FIG. 3 is a cross-sectional view of a coplanar-type TFT;

[0089]FIG. 4 is a cross-sectional view of a reverse stagger-type TFT;

[0090]FIG. 5 is a block diagram of an in-line-type coating filmdeposition unit used in a first embodiment in accordance with thepresent invention;

[0091]FIG. 6 is a block diagram of another in-line-type coating filmdeposition unit used in a first embodiment in accordance with thepresent invention;

[0092]FIG. 7 is a block diagram of a silicon-coating film depositionunit used in a first embodiment in accordance with the presentinvention;

[0093]FIG. 8 is a block diagram of another silicon-coating filmdeposition unit used in a first embodiment in accordance with thepresent invention;

[0094]FIG. 9 is a flow chart illustrating a method for metal-platingonto an ITO coating film surface;

[0095]FIG. 10 is a cross-sectional view of a production step of acoplanar-type TFT using an insulating layer containing an impurity inaccordance with the present invention;

[0096]FIG. 11 is a cross-sectional view of a production step of areverse stagger-type TFT using an insulating layer containing animpurity in accordance with the present invention;

[0097]FIG. 12 is a block diagram of a solution coating unit used in afirst embodiment in accordance with the present invention;

[0098]FIG. 13 is an outlined schematic view illustrating a state of thesolution coating unit of FIG. 12 after spin coating;

[0099]FIG. 14 is a block diagram of another solution coating unit inaccordance with the present invention;

[0100]FIG. 15 is an enlarged partial view of the solution coating unitshown in FIG. 14;

[0101]FIG. 16 is an enlarged partial view of the solution coating unitshown in FIG. 14;

[0102]FIG. 17 is a schematic view of a TFT substrate forming a liquidcrystal display device;

[0103]FIG. 18 is an enlarged plan view of a portion of a pixel regionindependently formed on an active matrix substrate for a liquid crystaldisplay device in accordance with a second embodiment of the presentinvention;

[0104]FIG. 19 is a cross-sectional view taken along section I-I′ of FIG.18;

[0105]FIG. 20 is a cross-sectional view illustrating a method for makingthe active matrix substrate shown in FIG. 19;

[0106]FIG. 21 is a cross-sectional view illustrating the steps performedafter the steps shown in FIG. 20;

[0107]FIG. 22 is an enlarged plan view of a portion of a pixel regionindependently formed on an active matrix substrate for a liquid crystaldisplay device in accordance with a third embodiment of the presentinvention;

[0108]FIG. 23 is a cross-sectional view taken along section II-II′ ofFIG. 22;

[0109]FIG. 24 is a cross-sectional view illustrating the steps performedafter the steps shown in FIG. 20 in the production of the active matrixsubstrate shown in FIG. 22;

[0110] FIGS. 25(A) and 25(B) are enlarged longitudinal cross-sectionalviews near contact holes of a comparative example and an example inaccordance with the present invention, respectively;

[0111]FIG. 26 is a cross-sectional view of a structure in accordancewith a fourth embodiment of the present invention, taken along sectionII-II′ of FIG. 22;

[0112] FIGS. 27(A) to 27(E) are cross-sectional views of a method formaking the active matrix substrate shown in FIG. 26;

[0113] FIGS. 28(A) to 28(E) are cross-sectional views of the stepsperformed after the steps shown in FIG. 27;

[0114]FIG. 29 is an enlarged plan view of a portion of a pixel regionindependently formed on an active matrix substrate for a liquid crystaldisplay device in accordance with a fifth embodiment of the presentinvention;

[0115]FIG. 30 is a cross-sectional view taken along section III-III′ ofFIG. 29;

[0116] FIGS. 31(A) to 31(F) are cross-sectional views illustrating thesteps performed after the steps shown in FIG. 27 in the production ofthe active matrix substrate shown in FIG. 29;

[0117]FIG. 32 is an enlarged plan view of a portion of a pixel regionindependently formed on an active matrix substrate for a liquid crystaldisplay device in accordance with a sixth embodiment of the presentinvention;

[0118]FIG. 33 is a cross-sectional view taken along section IV-IV′ ofFIG. 32;

[0119] FIGS. 34(A) to 34(D) are cross-sectional views illustrating thesteps performed after the steps shown in FIG. 27 in the production ofthe active matrix substrate shown in FIG. 32;

[0120]FIG. 35 is an enlarged plan view of a portion of a pixel regionindependently formed on an active matrix substrate for a liquid crystaldisplay device in accordance with a seventh embodiment of the presentinvention;

[0121]FIG. 36 is a cross-sectional view taken along section V-V′ of FIG.35;

[0122] FIGS. 37(A) to 37(C) are cross-sectional views illustrating thesteps performed after the steps shown in FIG. 27 in the production ofthe active matrix substrate shown in FIG. 35;

[0123] FIGS. 38(A) and 38(B) are schematic views of active matrixsubstrates for liquid crystal display devices in accordance with anotherembodiment;

[0124] FIGS. 39(A) and 39(B) are enlarged longitudinal cross-sectionalviews near contact holes of a comparative example and an example inaccordance with the present invention, respectively;

[0125]FIG. 40 is a block diagram of a liquid crystal display deviceincluded in an electronic device in accordance with an eighth embodimentof the present invention;

[0126]FIG. 41 is an outlined cross-sectional view of a projector as anexample of the electronic device using the liquid crystal display deviceof FIG. 40;

[0127]FIG. 42 is a schematic view of a personal computer as anotherexample of the electronic device;

[0128]FIG. 43 is an assembly view of a pager as a further example of theelectronic device; and

[0129]FIG. 44 is a schematic view of a liquid crystal display deviceprovided with a TCP.

BEST MODE FOR CARRYING OUT THE INVENTION

[0130] The present invention will now be described in detail withreference to the drawings.

First Embodiment

[0131] (Illustration of Thin Film Device Structure)

[0132] Two examples of thin film devices including TFTs are shown inFIGS. 3 and 4.

[0133]FIG. 3 is a cross-sectional view of a TFT using a coplanar-typepolycrystalline silicon. An insulating underlayer 12 is formed on aglass substrate, and a polycrystalline silicon TFT is formed thereon. InFIG. 3, the polycrystalline silicon layer 14 comprises a source region14S and a drain region 14D which are highly doped with an impurity, anda channel region 14C therebetween.

[0134] A gate insulating film 16 is formed on the polycrystallinesilicon layer 14 and a gate electrode 18 and a gate line (not shown inthe drawing) are formed thereon. A pixel electrode 22 composed of atransparent electrode film is connected to the drain region 14D throughan opening section formed in an interlevel insulating film 20 and thegate insulating film 16 thereunder, and a source line 24 is connected tothe source region 14S. A topmost protective film 26 may be omitted. Theinsulating underlayer 12 is provided for the purpose of prevention ofcontamination from the glass substrate 10 and of conditioning of thesurface for forming the polycrystalline silicon film 14, and may beomitted in some cases.

[0135]FIG. 4 is a cross-sectional view of a reverse stagger-typeamorphous silicon TFT. An insulating underlayer 32 is formed on a glasssubstrate 30, and an amorphous silicon TFT is formed thereon. Theinsulating underlayer 32 is often omitted. In FIG. 4, a layer or aplurality of layers of gate insulating films 36 are formed under a gateelectrode 34 and a gate line connected thereto. On the gate electrode34, an amorphous silicon channel region 38C is formed, and a sourceregion 38S and a drain region 38D are formed by diffusing an impurityinto the amorphous silicon. A pixel electrode 40 is electricallyconnected to the drain region 38D through a metal lead layer 42, and asource line 44 is electrically connected to the source region 38S. Themetal lead layer 42 and the source line are simultaneously formed.

[0136] A channel protective film 46 is formed on the channel region 38Cto protect the channel region 38C during etching of the source region38S and the drain region 38D, and may be omitted in some cases.

[0137]FIGS. 3 and 4 show basic TFT structures, and these structures mayhave a very wide range of modifications. For example, in order toincrease the aperture ratio in the coplanar-type TFT in FIG. 3, a secondinterlevel insulating film may be provided between the pixel electrode22 and the source line 24 to decrease the gap between the pixelelectrode 22 and the source line 24. Further, in order to decrease thewiring resistance of the gate line not shown in the drawing and thesource line 24 which are connected to the gate electrode 18 and toincrease the wiring length, the gate line and the source line may beformed of multiple layers. A light shielding layer may be formed on orunder the TFT element. In the reverse stagger-type TFT in FIG. 4, thewiring lines and the insulating film may be formed of multiple layersfor the purpose of improvement in the aperture ratio, a decrease in thewiring resistance and a decrease in defects.

[0138] Most of these modifications to the basic structures in FIGS. 3 or4 involve an increase in the number of thin layers deposited to form theTFT.

[0139] The following example shows a case in which various thin films inthe thin film monolithic structures shown in FIGS. 3 and 4 are formed bycoating films which require no vacuum system.

[0140] (Method for Forming Insulating Coating Film)

[0141]FIG. 1 shows a coating film deposition unit which forms a thinfilm, e.g. an insulating film, by applying and annealing a solution. Thesolution which becomes the insulating film by annealing after coatingcontains a polysilazane (generic name for polymers having Si-N bonds). Atypical polysilazane is polyperhydrosilazane represented by[SiH₂NH]_(n), wherein n is an integer. The compound is commerciallyavailable under the commercial name “Tonen Polysilazane”, which ismanufactured by Tonen Corporation. If alkyl groups, e.g. methyl groupsor ethyl groups, are substituted for hydrogen atoms in [SiH₂NH]_(n) thecompound is called organic polysilazane to distinguish it from inorganicpolysilazane. In this embodiment, it is preferable that inorganicpolysilazanes be used.

[0142] After a polysilazane is mixed with a solvent such as xylene, thesolution is applied onto a substrate by spin coating. The coating filmis converted to SiO₂ by annealing in a steam- or oxygen-containingatmosphere.

[0143] A film for comparison is a spin-on-glass (SOG) film which isconverted to an insulating film by annealing after coating. The SOG filmis composed of a polymer having siloxane bonds as a basic structure. TheSOG polymers include organic polymers having alkyl groups and inorganicpolymers not having alkyl groups, and alcohols and the like are used assolvents. The SOG film is used as an interlevel insulating film in anLSI for the purpose of planarization. The organic SOG film is readilyetched during an oxygen plasma process, whereas the inorganic SOG filmreadily forms cracks even if it has a thickness of several hundredangstroms, hence these films are not used as a single layer ofinsulating film, but are used as a planarization layer on a CVDinsulating film.

[0144] In contrast, polysilazane has high crack resistance and oxygenplasma resistance, and can be used as a single layer of insulating filmhaving an appropriate thickness. A case using polysilazane will now bedescribed.

[0145] In the present invention, at least one layer, and preferably aplurality of layers, in the thin film monolithic structure are formed ofcoating films other than the SOG film which has siloxane bonds as abasic structure. Additional SOG films can be used within the rangesatisfying the above condition.

[0146] In FIG. 1, a loader 101 separately removes a plurality ofsubstrates stored in a cassette and moves the glass substrates onto aspin coater 102. In the spin coater 102, as shown in FIG. 12, asubstrate 132 is fixed by vacuum on a stage 130, and then a polysilazanesolution 138 is dropped onto the substrate 132 through a nozzle 136 of adispenser 134. A mixed solution of polysilazane and xylene is stored ina container called a canister at a solution storage section 105 shown inFIGS. 1 and 12. The mixed solution of polysilazane and xylene issupplied to the dispenser 134 from the solution storage section 105through a feeding pipe 140 and is coated onto the substrate. Then, asshown in FIG. 13, the polysilazane solution 138 is dispersed onto theentire surface of the glass substrate 132 by the rotation of the stage130. Most of xylene is evaporated in this process. A control section 106shown in FIG. 1 controls the speed and time of rotation of the stage 130to increase the speed to 1,000 rpm in several seconds, to maintain 1,000rpm for approximately 20 seconds, and to stop the rotation after severalseconds. In such a coating condition, the polysilazane coating film hasa thickness of approximately 7,000 angstroms. Next, the glass substrateis transferred to an annealing section 103 and annealed at a temperatureof 100 to 350° C. for 10 to 60 minutes in a steam atmosphere to modifythe polysilazane to SiO₂. A temperature control section 107 controls theannealing step. The length of the annealing section 103 and the capacityfor holding the substrates in the annealing section 103 is determined soas to match the tact? time of the spin coater 102 with the annealingtime in order to enhance the performance of the coating-type insulatingfilm deposition unit. Because the polysilazane solution contains, forexample, xylene, and because hydrogen and ammonia form during themodification, at least the spin coater 102 and the annealing section 103require a ventilating system 108. The glass substrate provided with theinsulating film formed during the annealing process is stored into acassette by an unloader 104.

[0147] The coating-type insulating film deposition unit of the presentinvention shown in FIG. 1 has a significantly simplified systemconfiguration compared to conventional CVD systems, and thus the priceof the unit is remarkably decreased. Further, the unit has a higherthroughput than the CVD systems, decreased maintenance, and a high networking rate. These advantages enables drastic cost reduction of liquidcrystal display devices.

[0148] The coating-type insulating film deposition unit shown in FIG. 1can form all the insulating films shown in FIG. 3; that is, theinsulating underlayer 12, the gate insulating layer 16, the interlevelinsulating film 20 and the protective film 26. When an additionalinsulating layer is formed between the pixel electrode 22 and the sourceelectrode 24, the formation of the coating film using the unit shown inFIG. 1 is particularly effective for planarization of the surface of theadditional insulating layer. The insulating underlayer 12 and theprotective film 26 may be omitted in some cases.

[0149] Because the gate insulating film 16 is an important insulatingfilm determining electrical characteristics of the TFT, interfacialcharacteristics between the film and the silicon film, as well as thefilm thickness and the film quality, must be controlled.

[0150] In order to achieve such control, it is preferred to clean thesurface of the silicon film 14 before forming the gate insulating film16 by coating, and to use a coating-type insulating film deposition unitshown in FIG. 2. The unit shown in FIG. 2 is provided with a firstannealing section 103A having the same function as the annealing sectionof the unit shown in FIG. 1, and a second annealing section 103B infront of an unloader 104. After the annealing in the first annealingsection 103A, the second annealing section 103B preferably performs anannealing process at a temperature of 400 to 500° C., which is higherthan the annealing temperature of the first annealing section 103A, for30 to 60 minutes, or an annealing process at a high temperature for ashort period, such as by lamp annealing or laser annealing.

[0151] As a result, the insulating films such as the gate insulatingfilm 16 are further densified and have improved film quality andinterfacial characteristics as compared to the annealing only in theannealing section shown in FIG. 1.

[0152] Regarding the interfacial characteristics, a CVD film formed in avacuum atmosphere can be easily controlled compared to the insulatingcoating film. When a high performance TFT is required, therefore, thegate insulating film may be formed of a CVD film and the otherinsulating films in the TFT may be formed of insulating coating films inaccordance with the present invention.

[0153] In the TFT structure in FIG. 4, the insulating underlayer 32, thegate insulating film 36 and the channel protective film 46 can use theinsulating coating film of the present invention.

[0154] (Method for Forming Silicon Coating Film)

[0155] Using a coating solution containing silicon particles, which isstored in the solution storage section 105 shown in FIGS. 1 or 2, asilicon coating film can be formed using the same unit shown in FIGS. 1or 2.

[0156] The size of the silicon particles contained in the coatingsolution ranges, for example, from 0.01 to 10 μm. The size of thesilicon particles is determined by the thickness of the silicon coatingfilm. In the silicon particles obtained by the present inventors,particles of approximately 1 μm occupy 10%, and those of 10 μm or lessoccupy 95%. The silicon particles having such a size distribution arefurther pulverized with a pulverizer to obtain silicon particles havinga desired size distribution.

[0157] The silicon particles having a given size distribution are storedin the solution storage section 105 as a suspension in a solvent such asalcohol. The suspension composed of the silicon particles and alcohol isdischarged onto a substrate transferred onto the spin coater 106 fromthe loader 105. The stage 130 is rotated under the same coatingcondition as in the insulating coating film to disperse the coating filmof the silicon particles on the substrate, wherein most of alcohol isevaporated.

[0158] Next, the substrate is annealed in the annealing section 103 orthe first annealing section 103A under the same annealing condition asin the insulating coating film. The silicon particles react with eachother to form a crystallized silicon film on the substrate.

[0159] In the case using the unit in FIG. 2, the substrate is furtherannealed in the second annealing section 103B at a higher temperaturethan that in the first annealing section 103A. It is preferable that theannealing be performed in a short time by laser annealing or lampannealing.

[0160] Reannealing in the second annealing section 103B improvescrystallinity and density in the silicon film and adhesion to otherfilms, as compared to the annealing only in the first annealing section103A.

[0161]FIGS. 5 and 6 are block diagrams of film deposition units forcontinuously forming a silicon coating film and an insulating coatingfilm.

[0162] In the film deposition unit in FIG. 5, a loader 101, a first spincoater 102A, a first annealing section 103A, a second annealing section103B, a second spin coater 102B, an annealing section 103 and anunloader 104 are in-line-connected. The first spin coater 102A isconnected with a first solution storage section 105A storing asuspension of silicon particles and alcohol and a first control section106A. The second spin coater 102B is connected with a second solutionstorage section 105B storing a mixed solution of polysilazane and xyleneand a second control section 106B.

[0163] When using the unit in FIG. 5, the number of loading andunloading steps each decreases once and the throughput is furtherimproved.

[0164] The film deposition unit in FIG. 6 is a modification of the filmdeposition unit in FIG. 5, in which the second annealing section 103B isplaced after the annealing section 103 for the insulating coating film.In this case, the silicon film provided with an insulating cap layer iscrystallized in the second annealing section 103B by laser annealing orthe like. Because the insulating layer decreases reflectance of thesilicon surface, the laser energy is effectively absorbed in the siliconfilm. Further, the silicon film has a smooth surface after the laserannealing.

[0165] The annealing section 103 and the second annealing section 103Bin FIG. 6 may be unified into a common annealing section. In this case,the common annealing section can simultaneously perform firing of theinsulating coating film and annealing for crystallization of the siliconfilm thereon.

[0166] (Another Method for Forming Silicon Coating Film)

[0167]FIG. 7 shows a coating-type silicon film deposition unit in whicha silicon film is formed by coating and annealing of a coating solution.Monosilane (SiH₄) and disilane (Si₂H₆) are used for forming a siliconfilm in a CVD process, whereas higher silanes such as disilane andtrisilane (Si₃H₈) are used in the present invention. Boiling points ofsilanes are −111.9° C. for monosilane, −14.5° C. for disilane, 52.9° C.for trisilane, and 108.1° C. for tetrasilane (Si₄H₁₀), respectively.Monosilane and disilane are therefore gaseous at room temperature andpressure, whereas higher silanes such as trisilane are liquid. Asdisilane is liquified at minus several tens ° C., it can be used as acoating film. Hereinafter, a case using trisilane will be primarilydescribed.

[0168] In FIG. 7, after glass substrates are separately taken out by aloader 201 from a cassette and transferred into a load lock chamber 202,the load lock chamber 202 is evacuated by a ventilating system 711.After evacuating at a given pressure, the glass substrate is transferredonto a spin coater 203 which is also evacuated at a similar pressure,and trisilane in a trisilane storage section 207 is applied onto theglass substrate through a dispenser. The spin coater 203 rotates at arate of 100 to 2,000 rpm for several seconds to 20 seconds to spin-coattrisilane. The glass substrate after spin-coating trisilane isimmediately transferred to a first annealing section 204 having asimilar reduced pressure as above, and annealed at 300 to 450° C. forseveral tens of minutes to form a silicon film with a thickness ofseveral hundred angstroms. Then, the glass substrate is transferred to asecond annealing section 205 having a similar reduced pressure as above,and annealed at a high temperature for a short time by laser or lampannealing. The silicon film is thereby crystallized. After this, theglass substrate is transferred to a load lock chamber 206, and istransferred to an unloader 207 to a cassette after the load lock chamber206 is released to atmospheric pressure with gaseous nitrogen.

[0169] Preferably, two ventilating systems 211 are provided, that is,one connected to the two load lock chambers 202 and 206 and the otherconnected to the spin coater 203 and the first and second annealingsections 204 and 205. The spin coater 203, the first annealing section204 and the second annealing section 205 are always evacuated by theventilating system 211 to maintain a reduced pressure (near 1.0 to 0.5atmospheres) of an inert atmosphere, in order to prevent leakage ofgaseous toxic silanes. The threshold limit value (TLV) of monosilane is5 ppm, and it is considered that higher silanes such as disilane havesimilar TLVs. Silanes spontaneously burn at room temperature in air andexplosively burn at high temperatures. Thus, at least the ventilatingsystem 211 connected to the spin coater 203 and to the first and secondannealing sections 204 and 205 is connected to an exhaust gas disposalunit 212 which makes silanes non-toxic. The processing chambers 201 to207 in FIG. 7 are coupled with each other with gate valves which openand close when the glass substrate is transferred so that gaseoussilanes do not flow into the two load lock chambers.

[0170] The main section of the spin coater 203 is substantially the sameas in FIG. 12, and in FIG. 7. Preferably the temperature at the stage,on which the glass substrate is fixed by vacuum, is controlled by atemperature controlling section 210. The temperature is controlled toroom temperature and preferably approximately 0° C. when usingtrisilane, or at −40° C. or less and preferably −60° C. or less whenusing disilane. It is preferable that the solution storage section 208for disilane or trisilane and a feed line (not shown in the drawing) becontrolled to a temperature similar to the stage temperature by thetemperature control section 210.

[0171] Disilane or trisilane must be applied as a liquid at atemperature lower than its boiling point. Because trisilane has a vaporpressure of approximately 0.4 atm at room temperature and pressure anddisilane has a vapor pressure of approximately 0.3 atm at −40° C. andordinary pressure, it is preferable that the temperature of the silaneand substrate be decreased as much as possible in order to reduce thevapor pressure as much as possible.

[0172] The spin coater 203 and the first and second annealing sections204 and 205 may be pressurized with an inert gas in order to furtherreduce the vapor pressure of disilane or trisilane and improve theuniformity of the coating film. As the boiling temperature of disilaneor the like increases in the pressurized state and the vapor pressuredecreases at a given temperature, the spin coater 203 can be set at atemperature higher than the above-mentioned temperature and near theroom temperature. In this case, it is preferable that each chamber has adouble layer structure in view of leakage of trisilane or the like, inwhich an outer structure is provided out of the pressurized structureand leaked silane or the like in the outer structure is evacuatedthrough another ventilating system. The exhaust gas is disposed in theexhaust gas disposal unit 212.

[0173] Also, silane gas remaining in the spin coater 203 and the firstand second annealing section 204 and 205 is evacuated by the ventilatingsystem 211.

[0174] In FIG. 8, the silicon film deposition unit shown in FIG. 7 andthe insulating film deposition unit shown in FIG. 1 arein-line-connected to each other. In other words, the spin coatingsection 102 and the annealing section 103 shown in FIG. 1 are introducedbetween the second annealing section 205 and the load lock chamber 206in FIG. 7.

[0175] In FIG. 8, the steps for crystallizing the silicon film in thesecond annealing section 205 by laser annealing are the same as thesteps in the unit shown in FIG. 7. The crystallized silicon film istransferred onto the spin coater 102 to apply a polysilazane orinorganic SOG film. The coating film is modified into an insulating filmin the annealing section 103.

[0176] The spin coater 203 and the first and second annealing sections204 and 205 are under reduced pressure of an inert gas atmosphere as inFIG. 7. The spin coater 102 for the insulating film and the annealingsection 103 are under ordinary pressure in FIG. 1, whereas those in FIG.8 are under reduced pressure of an inert gas atmosphere. These chambersare evacuated by the ventilating system 108.

[0177] The silicon film formed by the unit shown in FIG. 8 is notexposed to open air, because the insulating film is formed on thesilicon film in the inert atmosphere. The interface between the siliconfilm and the insulating film is therefore controlled to determinecharacteristics of the TFT element, resulting in improvement in thecharacteristics of the TFT element and uniformity of thesecharacteristics.

[0178] In FIG. 8 the insulating film on the silicon film is formed aftercrystallization of the silicon film. However, the insulating film may beformed after the first annealing step of the silicon film and thesilicon film may be crystallized after annealing of the insulating film.Also, in this case, the silicon film provided with the insulating caplayer is crystallized by laser annealing as in FIG. 6. Because theinsulating film decreases the reflectance of the silicon surface, laserenergy is effectively absorbed in the silicon film. The silicon film hasa smooth surface after the laser annealing.

[0179] (Method for Diffusing Impurity into Silicon Coating Film)

[0180] Although an impurity may be diffused into a silicon film using aconventional ion implanting system, it is preferable that an insulatinglayer containing an impurity be applied onto the silicon layer and thenthe impurity be diffused into the underlying silicon film.

[0181] The insulating layer containing the impurity may be formed by theunit shown in FIG. 2. In this embodiment, an SOG film containingphosphorus glass or boron glass is applied as a coating film containingan impurity. When forming an n-type high-impurity region, the SOG filmas a coating film containing an impurity is formed using a solutioncomposed of a siloxane polymer and an ethanol or ethyl acetate solvent(Si content: several wt %), and containing several hundred μg of P₂O₅per 100 ml of solution.

[0182] In this case, the coating solution is stored in the solutionstorage section 105 in FIG. 2 and applied onto the substrate by the spincoater 102. The substrate on the spin coater 102 is rotated at severalthousand rpm to obtain an SOG film with a thickness of several thousandangstroms. The coating film containing the impurity is annealed at 300to 500° C. in the first annealing section 103A to form a phosphorusglass film containing several mol percent of P₂O₅. The TFT substrateprovided with the phosphorus glass film is annealed in the secondannealing section 103 at a high temperature for a short time by laserannealing, such that the impurity in the SOG film is diffused into theunderlying silicon film and a high impurity region is formed in thesilicon film. The TFT substrate is stored into a cassette by theunloader 104.

[0183] In the formation of the source and drain regions, both thecoating step and the annealing step at a high temperature for a shorttime can be completed within one minute, resulting in high productivity.Although the annealing step requires several tens of minutes, the tacttime can be reduced by optimizing the length and structure of theannealing oven.

[0184]FIGS. 10 and 11 are cross-sectional views of TFTs provided withthe coating film containing the impurity. FIG. 10 shows a coplanar-typeTFT corresponding to that in FIG. 3, in which an insulating underlayer12 is formed on a glass substrate 14, and a silicon layer 14 ispattern-formed thereon. A gate insulating film 16 is removed by etchingusing a gate electrode 18 as a mask, a silicon layer is temporallyexposed in regions which will be a source and a drain. The coating film50 containing the impurity is formed so as to come into contact with thesource and drain regions 14S and 14D in the silicon film. Phosphoruscontained in the coating film 50 is diffused into the silicon film bythe high-temperature, short-time annealing step and n-type source anddrain regions 14S and 14D having sheet resistances of 1 KΩ/□ are formed.

[0185] As shown in the cross-sectional view of the TFT shown FIG. 3, thefollowing steps include forming an interlevel insulating film, providinga contact hole, forming a pixel electrode and forming source wiring. Inthe formation of the interlevel insulating film, the interlevelinsulating film may be formed of a coating film after the coating film50 containing the impurity is removed, or the interlevel insulating filmmay be formed on the coating film 50 containing the impurity. As themethod for forming the interlevel insulating film on the coating film 50containing the impurity forms two insulating layers, the occurrence ofshort-circuits between the source line and the gate line in the liquidcrystal display device is decreased.

[0186]FIG. 11 shows a reverse stagger-type TFT corresponding to that inFIG. 4, in which an insulating underlayer 32 is formed on a glasssubstrate 30, and a gate electrode 35 is formed thereon. A silicon layer33 is pattern-formed through a gate insulating film. An insulating film52 functions as a protective film in the channel region and also as amask to impurity diffusion, and is formed of an insulating coating film.

[0187] An insulating film 54 containing an impurity is formed as aninsulating coating film in contact with the insulating film 52 as themask and regions of the silicon film 33 which will be a source region33S and a drain region 33D. When the insulating film 54 containing theimpurity is annealed at a high temperature for a short time, phosphoruscontained in the insulating film is diffused into the silicon film 33and n-type source and drain regions 33S and 33D having sheet resistancesof approximately 1 KΩ/□ are formed.

[0188] As shown in the cross-sectional view of the TFT shown FIG. 4,after the insulating film 54 containing the impurity is removed, a pixelelectrode, source wiring, a drain electrode and connecting sections areformed in that order.

[0189] In accordance with the present invention, the source and drainregions in the coplanar-type TFT are formed by forming a coating filmand the succeeding high-temperature, short-time annealing instead of aconventional ion implanting or an ion doping. Hence a TFT can be madeusing an inexpensive unit having a high throughput. In the reversestagger-type TFT shown in FIG. 4, the source and drain regions areformed by the high-temperature, short-time annealing step instead of theCVD process. Hence a liquid crystal display device can be made using aninexpensive unit having a high throughput as in the coplanar-type TFT.

[0190] (Method for Forming Conductive Coating Film)

[0191] A method for forming a conductive coating film by applying asolution containing conductive particles will now be described. Theconductive coating film is also made using the unit shown in FIG. 1 orFIG. 2. The liquid stored in the solution storage section 105 in FIG. 1or FIG. 2 is a suspension of conductive fine particles composed of metalor the like in, for example, an organic solvent. For example, adispersion of silver particles with a size of 80 to 100 angstroms in anorganic solvent, such as terpineol or toluene, is discharged onto thesubstrate through the spin coater 102. The substrate is rotated at 1,000rpm to spin-coat the coating solution on the substrate. The substrate isannealed at 250 to 300° C. in the annealing section in FIG. 1 or thefirst annealing section in FIG. 2 to form a conductive film with athickness of several thousand angstroms. Examples of conductivematerials include Au, Al, Ni, Co, Cr and ITO, and a conductive film canbe formed of particles of these materials using the conductive coatingfilm deposition unit.

[0192] Because the resulting conductive film is an aggregate of fineparticles and is very active, the spin coater 102, the annealing sectionor the first annealing section 103A must be in an inert gas atmosphere.

[0193] The resistance of the conductive coating film will be greater byone order of magnitude than the bulk resistance. In this case, theconductive coating film may be further annealed at 300 to 500° C. in thesecond annealing section 103B shown in FIG. 2 to decrease the resistanceof the conductive film. At the same time, the contact resistance of thesource region of the TFT with the source line formed of the conductivecoating film, and the contact resistance of the drain region with thepixel electrode formed of the conductive coating film, can be decreased.Introduction of a high-temperature, short-time annealing step by lamp orlaser annealing will further decrease the resistance of the conductivecoating film and the contact resistances. Further, a plurality of layerscomprising different metals may be formed in order to improvereliability. Since Ag is relatively easily oxidized in air, theformation of an Al or Cu layer, which is slightly oxidized in air, onthe Ag layer is preferable.

[0194] (Method for Forming Transparent Electrode)

[0195] A method for a transparent electrode using an ITO coating filmwill now be described. The ITO coating film may also be formed using theunit shown in FIG. 2. The coating solution used in this embodimentcontains 8% of a mixture of an organic indium and an organic tin in aratio of 97:3 in xylene (for example, manufactured by Asahi Denka KogyoK.K., trade name: ADEKA ITO coating film/ITO-130L). The ratio of theorganic indium to the organic tin in the coating solution may be in arange from 99:1 to 90:10. The coating solution is stored in the solutionstorage section 105 in FIG. 2.

[0196] The coating solution is discharged onto the substrate by the spincoater 102 and spin-coated by the rotation of the substrate.

[0197] The annealing conditions of the coating film were as follows.First, the substrate was annealed in an air or oxygen atmosphere at 250°C. to 450° C. for 30 minutes to 60 minutes in the first annealingsection shown in FIG. 2. Next, it was annealed in a hydrogen-containingatmosphere at 200° C. to 400° C. for 30 minutes to 60 minutes in thesecond annealing section 103B. As a result, organic components areremoved and a mixed film (ITO film) composed of indium oxide and tinoxide is formed. After the above-mentioned annealing steps, the ITO filmwith a thickness of approximately 500 angstroms to 2,000 angstroms has asheet resistance of 10²Ω per sheet to 10⁴Ω per sheet and a lighttransmittance of 90% or more, and exhibits satisfactory characteristicsas the pixel electrode. Although the sheet resistance of the ITO filmafter the first annealing step is of the order of 10⁵Ω per sheet to 10⁶Ωper sheet, the sheet resistance after the second annealing stepdecreases to the order of 10²Ω per sheet to 10⁴Ω per sheet.

[0198] Regarding the formation of the ITO coating film, the ITO film andthe insulating coating film can be formed by an in-line process usingthe unit shown in FIG. 5 or FIG. 6. The active ITO film surface cantherefore be immediately protected with the insulating film.

[0199] (Method for Forming Conductive Layer)

[0200] This method includes the formation of a metal plating layer onthe ITO coating film.

[0201]FIG. 9 is a flow chart of Ni plating on the ITO coating film. InStep 1 of FIG. 9, the ITO film is formed by the above-mentioned method.In Step 2, the surface of the ITO coating film is slightly etched toactivate the surface. In Step 3, as a pretreatment for Ni plating inStep 4, a Pd/Sn complex is adhered onto the surface of the ITO coatingfilm and then Pd is precipitated on the surface.

[0202] In the Ni plating of Step 4, Pd precipitated on the ITO coatingfilm is replaced with Ni to form a Ni plating layer by, for example, anelectroless plating process. The Ni plating layer becomes more dense byannealing in Step 4.

[0203] Finally, in Step 5, a noble metal plating layer, for example, anAu plating layer, as an antioxidant layer is formed on the Ni platinglayer to form a conductive layer.

[0204] Conductive layers other than the transparent electrode can beformed from the ITO coating film base by forming plating layers.

[0205] (Coating Method other than Spin Coating)

[0206] FIGS. 14 to 16 show a coating unit which applies a solutionforming a thin film or a resist solution used as a mask in photoresistetching. In this embodiment, a resist is exemplified as the solution tobe coated. The coating unit can be also applied to the formation ofvarious coating films other than the resist coating.

[0207] In FIG. 14, a substrate 302 is fixed by vacuum on a stage 301.The resist is supplied to a dispenser head 304 through a feeding pipe306 from a solution storage section 307. The resist is applied onto thesubstrate 302 as numerous dots 303 from a plurality of nozzles 305provided on the dispenser head 307.

[0208]FIG. 15 is a detailed cross-sectional view of the nozzle 305. Thenozzle structure in FIG. 15 is similar to that of an ink jet printer,and the resist is discharged by vibration of a piezoelectric element.The resist reaches a cavity section 313 through an inlet section 311 anda supply port 312. A vibration plate 315 moves in cooperation withvibration of a piezoelectric element 314 in close contact with thevibration plate 315 and the volume in the cavity 313 decreases orincreases. When the volume in the cavity 313 decreases, the resist isdischarged from the nozzle 316, and when the volume in the cavity 313increases the resist is supplied to the cavity 313 from the supply port312. As shown in FIG. 16, for example, a plurality of nozzles 316 aretwo-dimensionally arranged, the resist is applied onto the entiresubstrate as dots by relative movement of the substrate 302 or thedispenser 304, as shown in FIG. 14.

[0209] In FIG. 16, the array pitches of the nozzles 316 are severalhundred μm for the lateral pitch P1 and several mm for the longitudinalpitch P2. The nozzle 316 has a bore of several tens of μm to severalhundred μm. The volume of the resist discharged in a cycle ranges fromseveral tens of ng to several hundred ng, and the diameter of thedischarged droplets ranges from several tens of μm to several hundredμm.

[0210] The applied resist dot has a circular shape of several hundred μmimmediately after it is discharged from the nozzle 305. When applyingthe resist onto the entire substrate, the pitch of the dots 303 is setto several hundred μm and the substrate is rotated at several hundred toseveral thousand rpm for several seconds to form a coating film having auniform thickness. The thickness of the coating film can be controlledby the bore of the nozzle 316 and the pitch of the dots 303, as well asthe rotation rate and time of the substrate.

[0211] The resist coating process is an ink jet-type liquid coatingprocess and the resist is applied onto the entire substrate as dots.Because the substrate is moved or rotated so as to apply the resist tononresist portions between dots 303, the resist is effectively used.This process is also applicable to the formation of the insulating film,silicon film and conductive film instead of the coating process, andthus greatly contributes to cost reductions of liquid crystal displaydevices.

[0212] As the bore of the nozzle 316 can be further decreased in the inkjet-type liquid coating, the solution can be applied to form a linearpattern with a width of 10 to 20 μm. Use of this process in theformation of the silicon film or a conductive film permits directpatterning which requires no photolithographic process. When the designrequirement of the TFT is several tens of μm, a combination of thedirect patterning with a coating-type thin film deposition processpermits producing liquid crystal display devices without a CVD system, asputtering system, an ion implanting system, an ion doping system, anexposure system and an etching system. In other words, liquid crystaldisplay devices can be produced by an ink jet-type liquid coating unitin accordance with the present invention and an annealing unit such as alaser or lamp annealing unit.

[0213] In the first embodiment, although a TFT active matrix substrateis exemplified as a thin film device, the technologies in the firstembodiment are also applicable to other active matrix substrates,two-terminal and three-terminal elements as pixel switching elementscomposed of MIM (metal-insulator-metal) or MIS(metal-insulator-silicon). For example, the thin film monolithicstructure of an MIM active matrix substrate includes no semiconductorlayer, and consists of a conductive layer and an insulating layer, andthe present invention is also applicable to such a case. Further, thepresent invention is applicable to various display devices other thanactive matrix substrates, for example, an electro-luminescence device.In addition, the present invention is applicable to thin film deviceshaving various thin film monolithic structures comprising a conductivelayer, an insulating layer and a semiconductor layer, such assemiconductor devices including TFTs and DMDs (digital mirror devices).

[0214] Second to Seventh Embodiments will now be described in which thepresent invention is applied to active matrix substrates for liquidcrystal display devices and, in particular, pixel electrodes are formedby conductive coating films.

Second Embodiment

[0215]FIG. 18 is an enlarged partial plan view of pixel regions formedon an active matrix substrate for a liquid crystal display device, andFIG. 19 is a cross-sectional view taken along section I-I′ of FIG. 18.

[0216] In FIGS. 18 and 19, the active matrix substrate 400 for theliquid crystal display device is divided into a plurality of pixelregions 402 by data lines Sn, Sn+1 . . . and scanning lines Gm, Gm+1 . .. on an insulating substrate 410, and each of the pixel regions 402 isprovided with a TFT 404. The TFT 404 is provided with a channel region417 forming a channel between a source region 414 and a drain region416, a gate electrode 415 opposing to the channel region 417 with a gateinsulating film 413 formed therebetween, an interlevel insulating film421 formed on the top face of the gate electrode 415, a source electrode431 electrically connected to the source region 414 through a contacthole 421A formed in the interlevel insulating film 421, and a pixelelectrode 441 composed of an ITO film which is electrically connected tothe drain electrode 416 through a contact hole 421B formed in theinterlevel insulating film 421. The source electrode 431 is a part ofthe data lines Sn, Sn+1 . . . , and the gate electrode 415 is a part ofthe scanning lines Gm, Gm+1 . . . .

[0217] The pixel electrode 441, as well as the source electrode (dataline) 431, is formed on the interlevel insulating film 421. The pixelelectrode 441 is therefore formed such that the peripheries 441A and441B parallel to the data lines Sn and Sn+1 lie at positionsconsiderably inside the data lines Sn and Sn+1 to prevent the occurrenceof short-circuits between these electrodes.

[0218] FIGS. 20(A) to 20(D) and FIGS. 21(A) to 21(C) are cross-sectionalviews illustrating manufacturing steps of the active matrix substrate inthis embodiment.

[0219] In the production of such an active matrix substrate 400, first ageneral-purpose nonalkaline glass is prepared as the insulatingsubstrate 410, as shown in FIG. 20(A). After the insulating substrate410 is cleaned, a protective underlayer 411 composed of a silicon oxidefilm is formed on the insulating substrate 410 by a chemical vapordeposition (CVD) process or a physical vapor deposition (PVD) process.Examples of CVD processes include a low pressure CVD (LPCVD) process anda plasma enhanced CVD (PECVD) process. A typical PVD process is asputtering process. The protective underlayer 11 may be omitted in viewof impurities contained in the insulating substrate 410 and cleanlinesson the substrate surface.

[0220] Next, an intrinsic semiconductor film 406, such as a siliconfilm, which should be an active layer of the TFT 404, is formed. Thesemiconductor layer can be also formed by a CVD or PVD process. Theresulting semiconductor film 406 can be used as an amorphous siliconsemiconductor layer, such as a channel region of the TFT. Alternatively,as shown in FIG. 20(B), the semiconductor film 120 may be irradiatedwith optical energy such as laser light, or electromagnetic energy, topromote crystallization.

[0221] After a resist mask having a given pattern is formed, thesemiconductor film 406 is patterned using the resist mask to forminsular semiconductor films 412, as shown in FIG. 20(C). After formingthe semiconductor films 412, a gate insulating film 413 is formed by aPVD or CVD process.

[0222] A thin film as a gate electrode composed of an aluminum film orthe like is formed by a sputtering process. In general, the gateelectrode and gate lead are formed of a common metal material by thesame process. After depositing the gate electrode thin film, as shown inFIG. 20(D), gate electrodes 415 are formed by patterning. Scanning linesare also formed in this step. Impurity ions are introduced into eachsemiconductor film to form a source region 414 and a drain region 416. Asection not doped with impurity ions functions as a channel region 417.As the gate electrode 415 functions as a mask of ion implanting in thismethod, the TFT has a self-alignment structure in which the channelregion 417 is formed only under the gate electrode 415; however, the TFTmay be an offset gate structure or an LDD structure. Impurity ions maybe introduced by an ion doping process which implants hydride of theimpurity element and hydrogen using a mass-nonseparation-type ionimplanting system, or by an ion implanting system which implants onlypredetermined impurity ions using a mass-separation-type ion implantingsystem. Examples of material gases used in the ion doping processinclude hydrides of implanted impurities, such as phosphine (PH₃) anddiborane (B₂H₆) which are diluted in hydrogen to a concentration ofapproximately 0.1%.

[0223] Next, as shown in FIG. 21(A), an interlevel insulating film 421composed of a silicon oxide film is formed by a CVD or PVD process.After ion implantation and forming the interlevel insulating film 421,the interlevel insulating film 421 is annealed at a temperature of 350°C. or less for several tens of minutes to several hours in a giventhermal environment to activate the implanted ions and to bake theinterlevel insulating film 421.

[0224] Next, as shown in FIG. 21(B), contact holes 421A and 421B areformed at positions of the interlevel insulating film 421 correspondingto the source region 414 and the drain region 416. An aluminum film orthe like is formed by a sputtering process, and patterned to form asource electrode 431. A data line is also formed in this step.

[0225] Next, as shown in FIG. 21(C), an ITO film 408 is formed on theentire interlevel insulating film 421 by a coating process.

[0226] Various liquid or paste coating materials can be used in thecoating process. Among these coating materials, liquid materials areapplicable to a dipping or spin coating process, paste materials areapplicable to a screen printing process. The coating material used inthe Second Embodiment contains 8% of a mixture of an organic indium andan organic tin in a ratio of 97:3 in xylene (for example, manufacturedby Asahi Denka Kogyo K.K., trade name: ADEKA ITO coating film/ITO-130L),as in the First Embodiment, and is spin-coated on the top face of theinsulating substrate 410 (on the interlevel insulating film 20). Theratio of the organic indium to the organic tin in the coating materialmay be in a range from 99:1 to 90:10.

[0227] In the Second Embodiment, the film coated on the insulatingsubstrate 410 is annealed (baked) after removing the solvent and dryingit. After the film is annealed in an air or oxygen atmosphere at 250° C.to 450° C. for 30 minutes to 60 minutes, it is reannealed in a hydrogenatmosphere at 200° C. to 400° C. for 30 minutes to 60 minutes. As aresult, organic components are removed and a mixed film (ITO film) ofindium oxide and tin oxide is formed. After the above-mentionedannealing steps, the ITO film with a thickness of approximately 500angstroms to 2,000 angstroms has a sheet resistance of 10² Ω per sheetto 10⁴Ω per sheet and a light transmittance of 90% or more, and exhibitssatisfactory characteristics as the pixel electrode 441. Although thesheet resistance of the ITO film after the first annealing step is ofthe order of 10⁵Ω per sheet to 10⁶Ω per sheet, the sheet resistanceafter the second annealing step decreases to the order of 10²Ω per sheetto 10⁴ Ω per sheet.

[0228] After forming the ITO film 408 in such a manner, the pixelelectrode 441 is formed by patterning, as shown in FIG. 19, and thus aTFT 404 is formed in the pixel region 402. When the TFT 404 is driven bycontrol signals supplied through the scanning line Gm, image informationfor displaying is input to the liquid crystal cell encapsulated betweenthe pixel electrode 441 and a counter electrode (not shown in thedrawings) from the data line Sn through the TFT 404.

[0229] In the Second Embodiment as described above, as a liquid coatingmaterial is applied onto the insulating substrate 410 by a coatingprocess, such as a spin coating process, which is suitable for treatmentof large substrates, to form the ITO film for forming the pixelelectrode 441, the ITO film can be formed by an inexpensive system,without using a large film deposition system provided with a vacuumunit, such as a sputtering system.

[0230] In the coating method, the liquid or paste coating material fillsup the contact hole 421B as shown in FIG. 25(B) when it is applied ontothe interlevel insulating film 421. The surface shape of the resultingpixel electrode 441 is only slightly affected by the unevenness of thelayers thereunder. As a result, a flat pixel electrode 441 (conductivefilm) with no surface steps can be formed, rubbing can be stablyachieved, and the occurrence of reverse-tilt domains can be prevented.According to the Second Embodiment, the display quality is improved.

[0231] In contrast, when the pixel electrode is formed by an ITOsputtering film 450 as shown in FIG. 25(A), the resulting ITO sputteringfilm 450 is formed according to the steps of the surface thereunder.Such steps on the ITO sputtering film 450 result in unstable rubbing andthe occurrence of reverse-tilt domains, and thus decrease displayquality. Further, because it is difficult to form the ITO sputteringfilm so that it fills up the entire contact hole 421B, an opening isformed there. Such an opening also results in unstable rubbing and theoccurrence of reverse-tilt domains. Accordingly, it is useful to form apixel electrode 441 by an ITO coating film, as shown in FIG. 25(B).

Third Embodiment

[0232]FIG. 22 is an enlarged partial plan view of pixel regions formedon an active matrix substrate for a liquid crystal display device, andFIG. 23 is a cross-sectional view taken along section II-II′ of FIG. 22.

[0233] In FIGS. 22 and 23, differences between the thin film deviceconfiguration on the active matrix substrate 401 for the liquid crystaldisplay device in accordance with the Third Embodiment and the thin filmdevice configuration on the active matrix substrate 400 for the liquidcrystal display device in accordance with the Second Embodiment are asfollows.

[0234] The Third Embodiment employs a double-layer-structure interlevelinsulating film including a lower interlevel insulating film 421 formedon a gate electrode 415 and an upper interlevel insulating film 422formed on the lower interlevel insulating film 421. A source electrode431 is therefore formed on the lower interlevel insulating film 421 andis electrically connected to a source region 414 through a contact hole421A in the lower interlevel insulating film 421.

[0235] On the other hand, a pixel electrode is formed on the upperinterlevel insulating film 422, and is electrically connected to a drainregion 416 through a contact hole 422A in the upper interlevelinsulating film 422 and the lower interlevel insulating film 421.Because the pixel electrode 441 and the source electrode 431 are formedon different layers from each other, these electrodes do notshort-circuit each other.

[0236] In the Third Embodiment, as shown in FIG. 22, two peripheralsides 441A and 441B, parallel to data lines Sn and Sn+1, respectively,of the pixel electrode 441 in each pixel region 402 lie above the datalines Sn and Sn+1. Further two peripheral sides 441C and 441D, parallelto scanning lines Gm and Gm+1, respectively, of the pixel electrode 441lie above the scanning lines Gm and Gm+1 . In other words, a part of thepixel electrode 441 is formed on the data lines Sn and Sn+1 and thescanning lines Gm and Gm+1 . No gap is therefore formed between the fourperipheral sides 441A to 441D and the data lines Sn and Sn+1 or thescanning lines Gm and Gm+1 in the plan view. As a result, the data linesSn and Sn+1 and the scanning lines Gm and Gm+1 function as a blackmatrix, and high quality display can be achieved without providingadditional steps for forming a black matrix layer.

[0237] The manufacturing process of such an active matrix substrate 401also include the steps shown in FIGS. 20(A) to 20(D) for the SecondEmbodiment. The following steps after the steps shown in FIGS. 20(A) to20(D) will be described with reference to FIGS. 24(A) to 24(D).

[0238] As shown in FIG. 24(A), after forming a source region 414, adrain region 416, a channel region 417, a gate region 413 and a gateelectrode 415, a lower interlevel insulating film 421 composed of asilicon oxide film is formed by a CVD or PVD process.

[0239] Next, as shown in FIG. 24(B), a contact hole 421A is formed at aposition of the lower interlevel insulating film 421, corresponding tothe source region 414. An aluminum film is formed by a sputteringprocess and then is patterned to form a source electrode 431 and datalines Sn, Sn+1 . . . .

[0240] Next, as shown in FIG. 24(C), an upper interlevel insulating film422 composed of a silicon oxide film is formed on the lower interlevelinsulating film 421 by a CVD or PVD process. A contact hole 422A isformed at positions of the lower interlevel insulating film 421 and theupper interlevel insulating film 422, corresponding to the drain region416.

[0241] Next, as shown in FIG. 24(D), an ITO film 409 is formed bycoating on the entire surface of the interlevel insulating film 422.

[0242] The coating film can be also formed with various liquid and pastecoating materials as in the First and Second Embodiments. Among thesecoating materials, liquid materials are applicable to a dipping or spincoating process, and paste materials are applicable to a screen printingprocess.

[0243] In the Third Embodiment, the resulting ITO coating film 409 issubjected to first and second annealing processes as described above todecrease its sheet resistance.

[0244] Then, the ITO film 409 is patterned to form a pixel electrode 441as shown in FIG. 23. As described with reference to FIG. 22, in eachpixel region 2, the ITO film 409 is patterned such that the fourperipheral sides 441A to 441D of the pixel electrode 441 lie above thedata lines Sn and Sn+1 and the scanning lines Gm and Gm+1. As the datalines and the scanning lines are generally formed of a metal film, thesedata lines and scanning lines can be used as a black matrix. As aresult, high quality display can be achieved without further steps.

[0245] Further, the pixel region 441 is expanded as much as possible soas to overlap with the data lines and the scanning lines, hence thepixel region 402 has a high aperture ratio. The display quality isfurther improved thereby.

[0246] In the Third Embodiment, because the ITO film for forming thepixel electrode 441 is formed on the insulating substrate 410 by a spincoating process (coating film deposition method) which is suitable fortreatment of a large substrate, using a liquid coating material, thepixel electrode 441 has, as shown in FIG. 10(B), a large thickness at anindented portion of the lower layer and a small thickness at aprotruding portion of the lower layer. As a result, unevenness due tothe data lines is not reflected on the surface of the pixel electrode441. The formation of a flat pixel electrode 441 without surface stepscan stabilize rubbing and prevent the occurrence of reverse-tiltdomains. Such advantages hold on the upper layer side of the scanninglines. The present invention therefore improves display quality.

[0247] Further, because a liquid coating material is applied onto theinsulating substrate 410 by a spin coating process, the ITO film forforming the pixel electrode 441 can be formed by an inexpensive filmcoating system, differing from a sputtering process requiring a largefilm deposition system provided with a vacuum unit.

[0248] Additionally, the coating method has excellent characteristicsfor covering steps, hence large unevenness of the contact holes 421A and422A in the lower and upper interlevel insulating films 421 and 422 doesnot affect the surface shape of the pixel electrode 441 (ITO film).Because the two interlevel insulating films, that is, the lowerinterlevel insulating film 421 and the upper interlevel insulating film422 are formed, a flat pixel electrode 441 without surface steps can beformed regardless of large unevenness due to the contact holes 421A and422A. In such a configuration, the pixel electrode 441 is directlyconnected to the drain region 416 and no repeater electrode (via)electrically connected to the drain region 416 is formed between thelower interlevel insulating film 421 and the upper interlevel insulatingfilm 422, resulting in simplified production steps.

[0249] In the formation of the pixel electrode in the Third Embodiment,although a spin coating process is employed to form the ITO film using aliquid coating material, the ITO film can be formed by a printingprocess using a paste coating material. As the paste coating materialcan also be applicable to a screen printing process, a paste coatingmaterial is applied onto only the region forming the pixel electrode441, followed by drying and annealing, and the printed region can beused as the pixel electrode 441 without further steps. Becausepatterning of the ITO by an etching process is not required in thiscase, the production costs can be drastically decreased.

[0250] In the Second and Third Embodiments, coplanar-type TFTs areexemplified, in which the surface shape of the pixel electrode 441 isgreatly affected by the contact holes in the interlevel insulating film.When the present invention is applied to the formation of a pixelelectrode on a lower layer having unevenness in a reverse stagger-typeTFT, the effect of such unevenness on the surface shape of the pixelelectrode can be removed.

Fourth Embodiment

[0251]FIG. 26 is a cross-sectional view taken along section II-II′ ofFIG. 22, showing a configuration according to the Fourth Embodimentwhich is different from that in FIG. 23.

[0252] The Fourth Embodiment also employs two interlevel insulatingfilms 420 composed of a lower interlevel insulating film 421 and anupper interlevel insulating film 422 deposited on the lower interlevelinsulating film 421.

[0253] The configuration shown in FIG. 26 is different from theconfiguration in FIG. 23 in that the pixel electrode 441 has a doublelayer structure consisting of an ITO sputtering film 446 (conductivesputtering film) formed on the upper interlevel insulating film 422 by asputtering process, and an ITO coating film 447 (conductive transparentcoating film) formed on the ITO sputtering film 446.

[0254] The ITO coating film 447 is therefore electrically connected tothe drain region 416 through the ITO sputtering film 446 lyingthereunder. Because the ITO sputtering film 446 and the ITO coating film447 are simultaneously pattern-formed as described below, these have acommon forming region.

[0255] Because other portions are the same as those in FIG. 23, the sameidentification numbers are used without detailed description.

[0256] The planar layout of the configuration of the Fourth Embodimentis the same as that of the Third Embodiment, shown in FIG. 22, and thusdata lines Sn, Sn+1 . . . and scanning lines Gm, Gm+1 . . . function asa black matrix. As a result, high quality display can be achievedwithout increasing steps.

[0257] In the Third Embodiment, the ITO coating film 447 in contact withthe drain region 416 tends to have a higher contact resistance comparedto the ITO sputtering film. In the Fourth Embodiment, the ITO coatingfilm 447 is electrically connected to the drain region 416 through theITO sputtering film 446, and such a configuration does not cause a highcontact resistance.

[0258] A method for making such an active matrix substrate 401 will nowbe described with reference to FIGS. 27(A) to 27(E) and FIGS. 28(A) to28(E). Because the FIGS. 27(A) to 27(E) are the same as FIGS. 20(A) to20(D) and FIG. 24(A) for the steps of the Third Embodiment,respectively, the description is omitted. Also, the FIGS. 28(B) and28(C) are the same as FIGS. 24(B) and 24(C), respectively, for the stepsof the Third Embodiment.

[0259]FIG. 28(A) shows a resist pattern-forming step before the step inFIG. 28(B). In order to form the source electrode 431 and the sourceline shown in FIG. 28(B), an aluminum film 460 is formed by a sputteringprocess in FIG. 28(A). A patterned resist mask 461 is formed on thealuminum film 460. The source electrode 431 and the data line, as shownin FIG. 28(B), are formed by etching the aluminum film 460 using theresist film 461.

[0260] Next, as shown in FIG. 28(C), the upper interlevel insulatingfilm 422 composed of a silicon oxide film is deposited on the lowerinterlevel insulating film 421 by a CVD or PVD process. After ionimplantation and forming the interlevel insulating films, the substrateis annealed in a given thermal environment at 350° C. or less forseveral tens of minutes to several hours to activate the implanted ionsand to bake the interlevel insulating film 420 (the lower interlevelinsulating film 421 and the upper interlevel insulating film 422). Acontact hole 422A is formed at positions, corresponding to the drainregion 416, in the lower interlevel insulating film 421 and the upperinterlevel insulating film 422.

[0261] Next, as shown in FIG. 28(D), an ITO sputtering film 446(conductive sputtering film) is formed on the entire interlevelinsulating film 420 composed of the lower interlevel insulating film 421and the upper interlevel insulating film 422 by a sputtering process.

[0262] Next, as shown in FIG. 28(E), an ITO coating film 447 (conductivetransparent coating film) is formed on the ITO sputtering film 446.

[0263] The ITO coating film 447 can be formed under the same processconditions as in the First to Third Embodiments. The liquid or pastecoating film applied on the top face in the Fourth Embodiment isannealed in an annealing chamber after the solvent is removed by drying.The coating film is annealed or fired at a temperature of 250° C. to500° C. and preferably 250° C. to 400° C. for 30 minutes to 60 minutesin air or an oxygen-containing or nonreducing atmosphere, and thenannealed at a temperature of 200° C. or more and preferably 200° C. to350° C. for 30 minutes to 60 minutes in a hydrogen-containingatmosphere. The temperature of the second annealing step is set to belower than that of the first annealing step to prevent thermaldegradation of the coating film stabilized in the first annealing step.By such annealing steps, organic components are removed, and the coatingfilm is converted to a mixed film (ITO coating film 447) of indium oxideand tin oxide. As a result, the ITO coating film 447 with a thickness ofapproximately 500 angstroms to 2,000 angstroms has a sheet resistance of10²Ω per sheet to 10⁴Ω per sheet and a light transmittance of 90% ormore, and this and the ITO sputtering film 446 can form a pixelelectrode 441 exhibiting satisfactory characteristics.

[0264] Next, the insulating substrate 410 is maintained in thenonreductive atmosphere used in the second annealing step or anonoxidative atmosphere such as a gaseous nitrogen atmosphere until thesubstrate temperature decreases to 200° C. or less, and taken out toopen air from the annealing chamber when the substrate temperaturereaches 200° C. or less. When the insulating substrate 410 is exposed toopen air after the temperature reached 200° C. or less, the coating filmhaving a decreased resistance by the thermal reduction during the secondannealing step is prevented from reoxidation and thus the ITO coatingfilm 447 has a low sheet resistance. It is more preferable that thetemperature when the insulating substrate 410 is taken out from theannealing chamber to open air be 100° C. or less in order to preventreoxidation of the ITO coating film 447. Because the specific resistanceof the ITO coating film 447 decreases as oxygen defects in the filmincrease, reoxidation of the ITO coating film 447 due to oxygen in airincreases the specific resistance.

[0265] After forming the ITO sputtering film 446 and the ITO coatingfilm 447 in such a manner, a resist film 462 is formed, and these filmsare collectively patterned with an etching solution, such as aqua regiaor a HBr solution, or by dry etching using CH₄ or the like, to form thepixel electrode 441 as shown in FIG. 26. A TFT is thereby formed in eachpixel electrode 402. When driving the TFT in response to a controlsignal supplied through the scanning line Gm, image information is inputinto the liquid crystal encapsulated between the pixel electrode 441 andthe counter electrode (not shown in the drawing) from the data line Snthrough the TFT to display a given image.

[0266] In this embodiment, the ITO coating film 447 is used to form thepixel electrode 441. Because the film deposition by coating exhibitsexcellent characteristics for covering the steps, a liquid or pastecoating material to form the ITO coating film 447 can satisfactorilycompensate unevenness on the surface of the ITO sputtering film 446caused by the contact hole 422. Further, the coating material is coatedsuch that the ITO coating film 447 has a large thickness at an indentedportion and a small thickness at a protruded portion. Unevenness due tothe data line 431 does not therefore replicate the surface of the pixelelectrode 441. The same relationship holds in the upper layer of thescanning line 415. Accordingly, a pixel electrode 441 having a flatsurface without steps can be formed, resulting in stable rubbing andprevention of the occurrence of reverse-tilt domains. The presentinvention therefore improves image quality.

[0267] In contrast, when forming the pixel electrode by only an ITOsputtering film 446 as shown in FIG. 39A, the ITO sputtering film 446 isreplicated by the steps on the surface on which the ITO sputtering film446 is formed. The steps formed on the surface of the ITO sputteringfilm 446 cause unstable rubbing and the occurrence of reverse-tiltdomains, and thus deteriorate display quality. Further, it is difficultto form the ITO sputtering film 446 so as to fill the entire contacthole 422A, hence an opening is inevitably formed. Such an opening alsocauses unstable rubbing and the occurrence of reverse-tilt domains. Theformation of the ITO coating film 447 therefore is useful.

[0268] As shown in the Fourth Embodiment, when the interlevel insulatingfilm 420 has a double layer structure for the purpose of forming thepixel electrode 441 and the source electrode 431 on differentinterlayers, the aspect ratio of the contact hole 422A increases;however, the ITO coating film 447 can form a flat pixel electrode 441regardless of this.

[0269] The ITO sputtering film 446 has a trend of poor adhesion to aresist mask compared to the ITO coating film 447; however, the resistmask 462 is formed on the ITO coating film 447 in this embodiment, andaccuracy of patterning is not deteriorated. A pixel electrode 441 havinga high definition pattern can therefore be formed.

Fifth Embodiment

[0270]FIG. 29 is an enlarged plan view of a part of a pixel regionformed on an active matrix substrate for a liquid crystal display inaccordance with the present invention, and FIG. 30 is a cross-sectionalview taken along section III-III′ of FIG. 29. In the Fifth Embodiment,parts having the same function as in the Fourth Embodiment are referredto with the same identification numbers, and a detailed descriptionthereof with reference to drawings is omitted. In FIG. 29, the activematrix substrate 401 for a liquid crystal display in accordance with theFifth Embodiment is also provided with a plurality of pixel electroderegions 402 formed by data lines 431 and scanning lines 415 on aninsulating substrate 410, and a TFT is formed on each of the pixelelectrode regions 402.

[0271] The planar layout in the Fifth Embodiment other than the ITOsputtering film is identical to the configuration shown in FIG. 22 forillustrating the Third and Fourth Embodiments, hence data lines Sn, Sn+1. . . and scanning lines Gm, Gm+1 . . . function as a black matrix. Highquality image display therefore can be achieved without additionalsteps.

[0272] Because in the Fifth Embodiment an ITO sputtering film 456 and anITO coating film 457 are separately patterned as described below incontrast to the Fourth Embodiment, their regional areas are differentfrom each other. That is, the regional area of the ITO coating film 457is larger than the regional area of the ITO sputtering film 456.

[0273] When forming the ITO coating film and the ITO sputtering film ona common region as in the Fourth Embodiment, these two ITO films can besimultaneously patterned. The resist mask is formed only on the ITOcoating film having excellent adhesiveness to the resist mask, and isnot formed on the ITO sputtering film having poor adhesiveness to theresist mask. High definition patterning can therefore be achieved.

[0274] In contrast, in the Fifth Embodiment, a resist mask must beformed also on the surface of the ITO sputtering film. When the regionalarea of the ITO coating film is larger than the regional area of the ITOsputtering film, the accuracy of patterning of the ITO coating filmhaving excellent adhesiveness to the resist mask determine a finalpattern. Hence high definition patterning can be achieved even if theITO sputtering film has poor adhesiveness to the resist mask.

[0275] The steps shown in FIGS. 31(A) to 31(C) for a manufacturingmethod of such an active matrix substrate is similar to FIGS. 27(A) to27(E) for the Fourth Embodiment. Thus, only the steps shown in FIGS.31(D) to 31(F) will now be described.

[0276] In FIG. 31(C), an upper interlevel insulating film 422 composedof a silicon oxide film is formed on a lower interlevel insulating film421, and then a contact hole 422A is formed.

[0277] Next, as shown in FIG. 31(D), an ITO film 456 (conductivesputtering film) is formed by a sputtering process on the entire surfaceof the interlevel insulating film 420 composed of the lower interlevelinsulating film 421 and the upper interlevel insulating film 422. Thesesteps is also identical to the Fourth Embodiment.

[0278] In the Fifth Embodiment, however, only the ITO sputtering film456 is patterned with an etching solution, such as aqua regia or a HBrsolution, or by dry etching using CH₄ or the like. After forming the ITOsputtering film 456, a resist mask 464 is formed as shown FIG. 31(D) andis patterned. The ITO sputtering film 456 is etched using the resistmask 464 such that the ITO sputtering film 456 remains in a region whichis narrower than the region of a pixel electrode 441 to be formed. AnITO coating film (conductive transparent coating film) is formed on thetop face of the ITO sputtering film 456. The coating materials describedin the above-mentioned Embodiments can be used for forming the ITOcoating film 457.

[0279] After forming the ITO coating film 457 in such a manner, a resistmask 462 is formed as shown in FIG. 31(F) and is patterned with anetching solution, such as aqua regia or a HBr solution, or by dryetching using CH₄ or the like to form a pixel electrode 441 as shown inFIG. 30.

[0280] The configuration in the Fifth Embodiment has similar advantagesto that in the Fourth Embodiment. In particular, although the ITOcoating film 457 in contact with a drain region has a higher contactresistance than the ITO sputtering film, the ITO coating film 457 in theFifth Embodiment is electrically connected to the drain region 416through the ITO sputtering film 456 to cancel such a high contactresistance. Because the ITO sputtering film can be thin, it can beetched within a short time without preventing patterning, regardless ofpoor adhesiveness to the resist mask 464. Because the ITO coating film457 having high accuracy for patterning determines final accuracy of thepixel electrode 40 for patterning, high accuracy patterning can beachieved.

Sixth Embodiment

[0281]FIG. 32 is an enlarged plan view of a part of a pixel regionformed on an active matrix substrate for a liquid crystal display inaccordance with the present invention, and FIG. 33 is a cross-sectionalview taken along section IV-IV′ of FIG. 30.

[0282] The arrangement in the Sixth Embodiment is characterized in thata pixel electrode 441 is composed of an ITO coating film (conductivetransparent coating film) 468 formed by coating on an upper interlevelinsulating film 422, and the ITO coating film 468 is electricallyconnected to a repeater electrode 466 composed of an aluminum filmformed on a lower interlevel insulating film 421 by a sputtering processthrough a contact hole 422A in the upper interlevel insulating film 422.The repeater electrode 466 is electrically connected to a drain region416 through a contact hole 421B in the lower interlevel insulating film421. As a result, the pixel electrode 441 is electrically connected tothe drain electrode 416 through the repeater electrode 466 lyingthereunder.

[0283] Because the repeater electrode 466 composed of an aluminum filmdoes not have light transmitting characteristics, the region for formingit is limited to the interior and periphery of the contact hole 421 soas not to decrease the aperture ratio.

[0284] The steps shown in FIGS. 27(A) to 27(E) for the Fourth Embodimentcan be employed for the manufacturing method of such an active matrixsubstrate 401. The succeeding steps after the step in FIG. 27(E) willnow be described with reference to FIGS. 34(A) to 34(D).

[0285] As shown FIG. 34(A), after contact holes 421A and 421B are formedat positions corresponding to a source region 414 and a drain region416, respectively, in the lower interlevel insulating film 421, analuminum film 460 (conductive sputtering film or metal film) is formedby sputtering to form a source electrode 431 and data lines. Next, aresist mask 470 is formed and the aluminum film 460 is patterned usingthe resist mask 470. As a result, as shown in FIG. 34(B), the sourceelectrode 431, the data lines and the repeater electrode 466 aresimultaneously formed.

[0286] Next, as shown in FIG. 34(C), an upper interlevel insulating film422 of a silicon oxide film is formed on the surface of the lowerinterlevel insulating film 421 by a CVD or PVD process. A contact hole422A is formed at a position corresponding to the repeater electrode 466(a position corresponding to the drain region 416) in the upperinterlevel insulating film 422.

[0287] Next, as shown in FIG. 34(D), an ITO coating film 468 (conductivetransparent coating film) is formed on the entire interlevel insulatingfilm 420 consisting of the lower interlevel insulating film 421 and theupper interlevel insulating film 422.

[0288] The coating material described in the above-mentioned embodimentscan be used for forming the ITO coating film 468.

[0289] After forming the ITO film 468 in such a manner, a resist mask462 is formed and patterned to form a pixel electrode 441 as shown inFIG. 33.

[0290] As shown in FIG. 32, data lines Sn, Sn+1 . . . and scanning linesGm, Gm+1 . . . function as a black matrix. Further, the aperture ratioof the pixel region 402 can be increased and a pixel electrode 441having a flat surface without steps can be formed. Hence rubbing isstabilized and the occurrence of reverse-tilt domains can be prevented.

[0291] Although the pixel electrode 441 composed of the ITO coating film468 has a higher contact resistance with the drain region 416 (siliconfilm) than the ITO sputtering film, the ITO coating film 468 in theSixth Embodiment is electrically connected to the drain region 416through the repeater electrode 466 composed of the aluminum film formedby sputtering to counter such a high contact resistance.

[0292] Although aluminum is used for the repeater electrode 466 in thisembodiment, use of a dual layer film composed of aluminum and a highmelting point metal can further decrease the contact resistance with theITO coating film 468. The high melting point metal, such as tungsten ormolybdenum, is difficult to oxidize as compared to aluminum, and even ifit comes into contact with the ITO coating film 468 containing a largeamount of oxygen, no oxidation occurs. The contact resistance betweenthe repeater electrode 466 and the ITO coating film 468 can therefore bereduced.

Seventh Embodiment

[0293]FIG. 35 is an enlarged plan view of a part of a pixel regionformed on an active matrix substrate for a liquid crystal display inaccordance with the present invention, and FIG. 36 is a cross-sectionalview taken along section V-V′ of FIG. 35.

[0294] The Seventh Embodiment includes a modified configuration ofSecond Embodiment shown in FIG. 18 and FIG. 19, in which a repeaterelectrode 480 achieves electrical connection between an ITO coating film441 and a drain region 416.

[0295] In FIG. 35, an active matrix substrate 401 in accordance with theSeventh Embodiment is also provided with a plurality of pixel regions402 formed by data lines 431 and scanning lines 416 on an insulatingsubstrate 410, and each of the pixel regions 402 is provided with a TFT(a nonlinear element for pixel switching). If only planarization of thepixel electrode and reduction of the contact resistance are intended,the following configuration is available.

[0296] As shown in FIG. 36, in the Seventh Embodiment, an interlevelinsulating film 421 is composed of one silicon oxide layer.

[0297] The pixel electrode 441 composed of the ITO coating film isformed on the top face of the repeater electrode 480 composed of analuminum film (conductive sputtering film or metal film) which is formedon the interlevel insulating film 421 by a sputtering process. The pixelelectrode 441 is therefore electrically connected to the drain region416 through the repeater electrode 480. Because the repeater electrode480 composed of an aluminum film does not have light transmittingcharacteristics, the region for forming it is limited to the interiorand periphery of the contact hole 421B.

[0298] Because the pixel electrode 441 and the source electrode 431 areformed between two common layers in the Seventh Embodiment, such thatthese two electrodes are not short-circuited (refer to FIG. 35 and FIG.36).

[0299] Such an active matrix substrate 401 is manufactured according tothe steps shown in FIGS. 27(A) to 27(B) for the Fourth Embodiment. Thesucceeding steps after FIG. 27(E) will now be described with referenceto FIGS. 37(A) to 37(C).

[0300] As shown in FIG. 37(A), contact holes 421A and 421B are formed atpositions corresponding to a source region 414 and a drain region 416,respectively, in the interlevel insulating film 421. After forming bysputtering an aluminum film 460 for forming the source electrode 431 anddata lines, a resist mask 470 is formed. Next, the aluminum film 460 ispatterned using the resist mask 470 to form the source electrode 431,the data lines and the repeater electrode 480 as shown in FIG. 37(B).

[0301] Next, as shown in FIG. 37(C), an ITO coating film 482 (conductivetransparent electrode) is formed on the entire top face of theinterlevel insulating film 421. The coating films used in theabove-mentioned embodiments can be used for forming the ITO coating film482.

[0302] After forming the ITO coating film 482 in such a manner, a resistmask 484 is formed and the ITO coating film 482 is patterned using theresist mask 484 to form a pixel electrode 441 as shown in FIG. 36.

[0303] Accordingly, a pixel electrode 441 having a flat surface withoutsteps can be formed, resulting in stable rubbing and prevention of theoccurrence of a reverse-tilt domain. Further, an increase in the contactresistance between the pixel electrode composed of the ITO coating filmformed by a coating process and the drain region 416 can be prevented.

[0304] The present invention is not limited the above-describedembodiments and can include various modifications within the scope ofthe present invention.

[0305] For instance, in the Sixth and Seventh Embodiments, the repeaterelectrodes 466 and 480, the source electrode 431 and the data lines aresimultaneously formed of the common metal film (aluminum film). Instead,when the interlevel insulating film 420 includes a lower interlevelinsulating film 421 and an upper interlevel insulating film 422, boththe pixel electrode 441 composed of the ITO film by a coating processand the repeater electrode 486 composed of a conductive sputtering filmmay be formed on the upper insulating film 422. Such a configuration canextend the region forming the pixel electrode 441, differing from theSixth Embodiment, and thus data lines and scanning lines function as ablack matrix. Because the repeating electrode 486 (conductive sputteringfilm) and the source electrode 431 are formed by different steps, thematerial for the repeating electrode 486 may be the same as or differentfrom the material for the source electrode 431.

[0306] In both the Sixth and Seventh Embodiments, although planar-typeTFTs are described in which the contact holes in the interlevelinsulating films greatly affect the surface shapes of the pixelelectrodes, the present invention can also be applied to a reversestagger-type TFT. When the pixel electrode is forced to be formed on anuneven surface, the surface of the pixel electrode formed of aconductive transparent coating film by a coating process as in thepresent invention is not affected by such unevenness.

[0307] For example, an ITO coating film is used as the pixel electrode441 in a reverse stagger-type TFT shown in FIG. 38(B) for the purpose ofplanarization of the surface of the pixel electrode 441. In the TFTshown in FIG. 38(B), a protective underlayer 411, a gate electrode 415,a gate insulating film 413, an intrinsic amorphous silicon film forminga channel region 417 and an insulating film 490 for protecting thechannel are deposited in that order on an insulating substrate 410.Source and drain regions 414 and 416 composed of a high concentrationn-type amorphous silicon film are formed on both sides of the insulatingfilm 490 for protecting the channel, and a source electrode 431 and arepeater electrode 492 composed of a sputtering film such as chromium,aluminum or titanium are formed on the source and drain regions 414 and416. Further, an interlevel insulating film 494 and a pixel electrode441 are formed thereon. Because the pixel electrode 331 is composed ofan ITO coating film, it has a flat surface. The pixel electrode 441 iselectrically connected to the repeater electrode 496 through a contacthole in the interlevel insulating film 441. Because the pixel electrode441 is electrically connected to the drain region 416 through therepeater electrode 496 composed of the sputtering film, the problem ofhigh contact resistance between the pixel electrode 441 composed of theITO coating film and the drain region 416 (silicon film) can be solved.Because the pixel electrode 441 and the source electrode 431 arearranged between different layers, these electrode does notshort-circuit. As a result, the pixel electrode 441 can be formed in awide range so as to cover the data lines and the scanning lines (notshown in the drawing). Hence the data lines and the scanning linesfunctions as a black matrix and the aperture ratio of the pixel regioncan be increased.

[0308] Although the ITO coating film for forming the pixel electrode isdeposited with a liquid coating material by a spin coating process, theITO coating film may be deposited using a paste coating material by aprinting process. Further use of the paste coating material enables ascreen printing process, in which the paste coating material is printedonly on the region to form the pixel electrode followed by drying andannealing, and the resulting film can be used as the pixel electrode.Because this case does not require patterning of the ITO film, theproduction costs can be drastically reduced.

[0309] Although only the pixel electrode is formed of a coating film inthe Second to Seventh Embodiments, any one of an insulating layer, aconductive layer and a semiconductive layer, as well as the pixelelectrode, can be, of course, formed of a coating film, as described inthe First Embodiment.

Eighth Embodiment

[0310] An electronic device formed of a liquid crystal display device inaccordance with any of the above-mentioned embodiments includes, asshown in FIG. 40, a display information source 1000, a displayinformation processing circuit 1002, a display driving circuit 1004, adisplay panel 1006 such as a liquid crystal panel, a clock generatingcircuit 1008 and an electric power circuit 1010. The display informationsource 1000 includes memories such as ROM and RAM, and a tuning circuitfor tuning and outputting the television signals, and output displayinformation such as video signals based on a clock from the clockgenerating circuit 1008. The display information processing circuit 1002processes and output the display information based on the clock from theclock generating circuit. The display information processing circuit1002 may include, for example, an amplification and polarity inversioncircuit, a circuit with parallel data input, a rotation circuit, a gammacorrection circuit and a clamping circuit. The display driving circuit1004 includes a scanning line driving circuit and a data line drivingcircuit and drives to display the liquid crystal panel 1006. Theelectric power circuit 1010 supplies electric power to theabove-mentioned circuits.

[0311] Examples of electronic devices having such a configurationinclude liquid crystal projectors as shown in FIG. 41, personalcomputers (PCs) as shown in FIG. 42, and engineering work stations(EWSs) responding to multimedia pagers as shown in FIG. 43 and portablephones, word processors, televisions, view finder-type and monitor-typevideo taperecorders, electronic notebooks, electronic desktopcalculators, car navigation systems, POS terminals, and apparatusesprovided with touch panels.

[0312] The liquid crystal projector shown in FIG. 41 is a projectiontype-projector using a transparent liquid crystal panel as a light valveand includes, for example, a three-plate prism-type optical system.

[0313] In the projector 1100 shown in FIG. 41, projection light emergingfrom a lamp unit 1102 provided with a white light source is divided intothree primary colors, R, G and B by a plurality of mirrors 1106 and twodichroic mirrors 1108 in a light guide 1104, and the three primarycolors are introduced to three color liquid crystal panels 1110R, 1110Gand 1110B for displaying their respective colors. The light beamsmodulated by the liquid crystal panels 1110R, 1110G and 1110B areincident on a dichroic prism 1112 from three directions. In the dichroicprism 1112, as the red R and blue B light beams are reflected by 90°,whereas the green G light beam travels straight, images of these colorsare combined and, thus, a color image is projected on a screen or thelike through a projection lens.

[0314] The personal computer 1200 shown in FIG. 42 includes a main body1204 provided with a key board 1202 and a liquid crystal display screen1206.

[0315] The pager 1300 shown in FIG. 43 includes a liquid crystal displayboard 1304, a light guide 1306 provided with a back light 1306 a, acircuit board 1308, a first shield plate 1310 and a second shield plate1312, two elastic conductors 1314 and 1316 and a film carrier tape 1318,which are provided in a metallic frame 1302. The two elastic conductors1314 and 1316 and the film carrier tape 1318 are provided for connectingthe liquid crystal display board 1304 to the circuit board 1308.

[0316] The liquid crystal display board 1304 is composed of a liquidcrystal encapsulated between two transparent substrates 1304 a and 1304b and forms at least a dot-matrix liquid crystal panel. One of thetransparent substrates may be provided with a driving circuit 1004 shownin FIG. 40, and additionally, a display information processing circuit1002. Circuits not mounted in the liquid crystal display board 1304 canbe mounted in the circuit board 1308 shown in FIG. 43 as an externalcircuit of the liquid crystal display board.

[0317] The pager configuration shown in FIG. 43 further requires acircuit board 1308, as well as the liquid crystal display board 1304,and when a liquid crystal display device is used as one unit in anelectronic device and when a display driving circuit is mounted onto atransparent board, the minimum unit of the liquid crystal display deviceis the liquid crystal display board 1304. Alternatively, the liquidcrystal display board 1305 fixed into the metallic frame 1302 can beused as a liquid crystal display device which is a part of an electronicdevice. Further a back-light-type liquid crystal display device can beformed by assembling the liquid crystal display board 1304, and a lightguide 1306 provided with a back light 1306 a into the metallic frame1302. Instead, as shown in FIG. 44, a tape carrier package (TCP) 1320,in which an IC chip 1324 is packaged onto a polyimide tape 1322 providedwith a metallic conductive film, may be connected to one of the twotransparent substrates 1304 a and 1304 b of liquid crystal display board1304 to be used as a liquid crystal display device as a part of theelectronic device.

1. A thin film device having a thin film monolithic structure comprisinga plurality of thin films including at least one insulating layer and atleast one conductive layer, wherein at least one of said thin films insaid thin film monolithic structure is formed of a coating film(excluding a spin-on-glass film having a basic structure comprisingsiloxane bonds), which is obtained by applying a solution containing aconstituent of said thin film followed by annealing.
 2. A thin filmdevice according to claim 1, wherein said thin film monolithic structurecomprises a semiconductor layer.
 3. A thin film device according toclaim 2, wherein said thin film monolithic structure comprises a thinfilm transistor comprising: a silicon semiconductor layer including asource region, a drain region and a channel region therebetween; a gateinsulating layer; and a gate electrode.
 4. A thin film device accordingto claim 3, wherein said thin film monolithic structure furthercomprises an insulating underlayer formed under said thin filmtransistor.
 5. A thin film device according to either claim 3 or 4,wherein said thin film monolithic structure further comprises: a sourceelectrode connected to said source region, a drain electrode connectedto said drain region, and at least one interlevel insulating film whichinsulates said gate electrode, said source electrode and said drainelectrode.
 6. A thin film device according to any one of claims 3 to 5,wherein said thin film monolithic structure further comprises aprotective insulating layer on said thin film transistor.
 7. A thin filmdevice according to any one of claims 3 to 6, wherein all of saidinsulating layers included in said thin film monolithic structure areformed of said coating film.
 8. A thin film device according to any oneof claims 4 to 6, wherein all of said insulating layers other than saidgate insulating layer are formed of said coating film.
 9. A thin filmdevice according to any one of claims 1 to 6, wherein at least two ofsaid thin films included in said thin film monolithic structure areformed of said coating film.
 10. A thin film device according to any oneof claims 1 to 9, wherein said at least one insulating layer is formedof a SiO₂ coating film which is obtained by applying a solutioncontaining a polymer having Si—N bonds and performing a first annealingprocess in an oxygen atmosphere.
 11. A thin film device according toclaim 10, wherein said at least one insulating layer is subjected to asecond annealing process after said first annealing process at atemperature higher than that in said first annealing process, so that aninterface is further cleaned compared to that after said first annealingprocess.
 12. A thin film device according to any one of claims 2 to 9,wherein said semiconductor layer comprises a silicon coating film whichis obtained by applying a solution containing silicon particles andperforming a first annealing process and includes an impurity.
 13. Athin film device according to claim 12, wherein said semiconductor layeris subjected to a second annealing process after said first annealingprocess at a temperature higher than that in said first annealingprocess, so that the crystallinity is improved compared to that aftersaid first annealing process.
 14. A thin film device according to anyone of claims 1 to 9, wherein said at least one conductive layer isformed of a conductive coating film obtained by applying a solutioncontaining conductive particles and performing a first annealingprocess.
 15. A thin film device according to claim 14, wherein said atleast one conductive layer is subjected to a second annealing processafter said first annealing process at a temperature higher than that insaid first annealing process, so that the resistance is reduced comparedto that after said first annealing process.
 16. A thin film deviceaccording to claim 14, wherein said conductive coating film is an ITOcoating film.
 17. A thin film device according to claim 16, wherein asurface of said ITO coating film is metal-plated.
 18. A thin film deviceaccording to any one of claims 13 to 17, wherein said at least oneconductive layer further comprises a conductive sputtering film formedon a contact face of said conductive layer by a sputtering process. 19.A thin film device according to claim 1, wherein said thin filmmonolithic structure further comprises a plurality of pixel switchingelements arranged at corresponding pixels formed near intersections of aplurality of data lines with a plurality of scanning lines, and pixelelectrodes connected thereto.
 20. A thin film device according to claim19, wherein each of said pixel switching elements is a thin filmtransistor.
 21. A thin film device according to claim 20, wherein saidthin film transistor comprises: a source region electrically connectedto one of said data lines, a gate electrode electrically connected toone of said scanning lines, and a drain electrode electrically connectedto one of said pixel electrodes, wherein said pixel electrode is formedof a conductive coating film.
 22. A thin film device according to claim21, wherein said conductive coating film is an ITO coating film.
 23. Athin film device according to either claim 21 or 22, wherein said thinfilm transistor further comprises an interlevel insulating film formedon the top face of said gate electrode, and said data line and saidpixel electrode are electrically connected to said source region andsaid drain region, respectively, through respective contact holes formedin said interlevel insulating film.
 24. A thin film device according toclaim 23, wherein said interlevel insulating film comprises a lowerinterlevel insulating film lying at the lower side and an upperinterlevel insulating film formed on said lower interlevel insulatingfilm, each of said data lines is electrically connected to said sourceregion through a first contact hole formed in said lower interlevelinsulating film, each of said pixel electrodes is electrically connectedto said drain region through a second contact hole formed in said lowerinterlevel insulating film and said upper interlevel insulating film,and the periphery of said pixel electrode lies above said data lines andsaid scanning lines.
 25. A thin film device according to either claim 23or 24, wherein each of said pixel electrodes formed of said conductivecoating film is electrically connected to said drain electrode through aconductive sputtering film.
 26. A thin film device according to claim25, wherein said conductive sputtering film is an ITO sputtering film.27. A thin film device according to either claim 25 or 26, wherein saidconductive coating film and said conductive sputtering film have acommon pattern.
 28. A thin film device according to either claim 25 or26, wherein the periphery of said conductive coating film lies outsidethe periphery of said conductive sputtering film.
 29. A thin film deviceaccording to either claim 25 or 26, wherein said conductive sputteringfilm and said data lines lie in a common layer and are formed of acommon metallic material.
 30. A thin film device according to eitherclaim 25 or 28, wherein said conductive sputtering film lies above saiddata lines.
 31. A thin film device according to claim 23, wherein saidinterlevel insulating film comprises a lower interlevel insulating filmlying at the lower side and an upper interlevel insulating film formedon said lower interlevel insulating film, a conductive sputtering filmformed on said upper interlevel insulating film, said conductivesputtering film and said data lines lying in the same layer, each ofsaid data lines is electrically connected to said source region througha first contact hole formed in said lower interlevel insulating film,said conductive sputtering film is electrically connected to said drainregion through a second contact hole formed in said upper interlevelinsulating film and said lower interlevel insulating film, and saidconductive coating film is deposited on said conductive sputtering film.32. A thin film device according to claim 23, wherein said interlevelinsulating film comprises a lower interlevel insulating film lying atthe lower side and an upper interlevel insulating film formed on saidlower interlevel insulating film, a conductive sputtering film formed onsaid lower interlevel insulating film, said conductive sputtering filmand said data lines lying in the same layer, each of said data lines iselectrically connected to said source region through a first contacthole formed in said lower interlevel insulating film, said conductivesputtering film is electrically connected to said drain region through asecond contact hole formed in said lower interlevel insulating film, andsaid conductive coating film is deposited on said upper interlevelinsulating film and electrically connected to said conductive sputteringfilm through a third contact hole formed in said upper interlevelinsulating film.
 33. A liquid crystal panel comprising: an active matrixsubstrate provided with a thin film device described in any one ofclaims 19 to 32, a counter substrate facing said active matrixsubstrate, and a liquid crystal layer encapsulated between said activematrix substrate and said counter substrate.
 34. An electronic devicecomprising the liquid crystal panel described in claim
 34. 35. A methodfor making a thin film device having a thin film monolithic structurecomprising a plurality of thin films including at least one insulatinglayer and at least one conductive layer; the manufacturing steps of atleast one of said thin films in said thin film monolithic structurecomprising: a step for applying a coating solution containing aconstituent of said thin film onto a substrate; and a step for forming acoating film (excluding a spin-on-glass film having a basic structurecomprising siloxane bonds) by annealing the coated surface on saidsubstrate.
 36. A method for making a thin film device according to claim35, wherein the manufacturing steps of said at least one insulatinglayer comprises: a first step applying a coating solution containing apolymer having Si-N bonds onto said substrate, and a second stepapplying a first annealing process to the coated surface in an oxygenatmosphere to form a SiO₂ insulating coating film; and wherein said atleast one insulating layer is formed of said insulating coating film.37. A method for making a thin film device according to claim 36,wherein said manufacturing steps further comprises a third step ofapplying a second annealing process to said substrate after said secondstep at a temperature higher than that in said first annealing process,so that the interface of said at least one insulating layer is furthercleaned compared to that after said first annealing process.
 38. Amethod for making a thin film device according to claim 37, wherein saidsecond annealing process is performed by laser annealing or lampannealing.
 39. A method for making a thin film device according to claim35, wherein said thin film monolithic structure further comprises asilicon semiconductor layer; and the manufacturing steps of said siliconsemiconductor layer comprises: a first step applying a coating solutioncontaining silicon particles onto said substrate, a second step applyinga first annealing process onto the coated surface to form a siliconcoating film, and a third step forming said silicon semiconductor layerby implanting an impurity into said silicon coating film.
 40. A methodfor making a thin film device according to claim 39, wherein a secondannealing process at a temperature higher than that in said firstannealing process is performed after said second annealing process so asto improve the crystallinity in said silicon coating film compared tothat after said first annealing process.
 41. A method for making a thinfilm device according to claim 40, wherein said second annealing processis performed by laser annealing or lamp annealing.
 42. A method formaking a thin film device according to any one of claims 39 to 41,wherein said third step further comprises: forming a layer containing animpurity by coating onto said silicon coating film, and heating saidlayer containing said impurity to diffuse said impurity into saidsilicon coating film.
 43. A method for making a thin film deviceaccording to claim 35, wherein said manufacturing steps of said at leastone conductive layer comprises: a first step applying a coating solutioncontaining conductive particles onto said substrate, and a second stepapplying a first annealing process onto the coated surface to form aconductive coating film; said at least one conductive layer being formedof said conductive coating film.
 44. A method for making a thin filmdevice according to claim 43, wherein a second annealing process at atemperature higher than that in said first annealing process isperformed after said second annealing process so as to reduce theresistance of said conductive coating film compared to that after saidfirst annealing process.
 45. A method for making a thin film deviceaccording to claim 44, wherein said second annealing process isperformed by laser annealing or lamp annealing.
 46. A method for makinga thin film device according to claim 35, wherein said manufacturingsteps of said at least one conductive layer comprises: a first annealingstep annealing said coated surface in an oxygen atmosphere or anonreductive atmosphere, and a second annealing step annealing saidcoated surface in a hydrogen atmosphere or a reductive atmosphere; saidat least one conductive layer being formed of a transparent conductivecoating film.
 47. A method for making a thin film device according toclaim 46, wherein the annealing temperature in said second annealingstep is set to a temperature lower than the annealing temperature insaid first annealing step.
 48. A method for making a thin film deviceaccording to either claim 46 or 47, wherein after said second annealingstep said substrate is maintained in a nonoxidative atmosphere until thetemperature of said substrate decreases to 200° C. or less.
 49. A methodfor making a thin film device according to any one of claims 46 to 48,wherein a coating solution containing indium (In) and tin (Sn) isapplied onto said substrate to form said transparent conductive coatingfilm by an ITO coating film.
 50. A method for making a thin film deviceaccording to claim 49, wherein said method further comprises a step formetal-plating on the surface of said ITO coating film after said secondannealing step.
 51. A method for making a thin film device according toclaim 49, wherein said method further comprises a step for forming aconductive sputtering film onto the contact face of said ITO coatingfilm by a sputtering process.
 52. A method for making a thin film deviceaccording to any one of claims 35 to 51, wherein in the coating step ofsaid solution, said solution is applied onto only the coating region onsaid substrate to form a patterned coating film on said substrate.
 53. Amethod for making a thin film device comprising: preparing a coatingsolution-dispenser head having a plurality of nozzles, and dischargingsaid coating solution onto only the coating region on a substrate whilechanging a relative position between said substrate and said pluralityof nozzles to form a patterned coating film on said substrate.
 54. Amethod for making a thin film device according to claim 53, wherein saida plurality of nozzles are independently controlled in dischargingstates or nondischarging states, and the relative position between saidsubstrate and said a plurality of nozzles is changed while controllingthe coating timing at individual nozzles.
 55. A method for making a thinfilm device according to either claim 53 or 54, wherein said coatingsolution is a resist solution, and said resist solution is applied inaccordance with a given pattern and then annealed to pattern-form aresist film.
 56. A method for making a thin film device according toeither claim 53 or 54, wherein said coating solution contains aconstituent of a thin film which is pattern-formed onto said substrate,and said coating solution is applied in accordance with a given patternand then annealed to pattern-form said thin film.
 57. A method formaking a thin film device according to claim 56, wherein said thin filmis a conductive layer having a given pattern.
 58. A method for making athin film device according to claim 56, wherein said thin film is aninsulating layer having a given pattern.
 59. A method for making a thinfilm device according to claim 58, wherein a contact hole issimultaneously formed in said insulating layer.